Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012-2014 |
| 4 | * Texas Instruments Incorporated, <www.ti.com> |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 5 | */ |
| 6 | #ifndef _PSC_DEFS_H_ |
| 7 | #define _PSC_DEFS_H_ |
| 8 | |
| 9 | #include <asm/arch/hardware.h> |
| 10 | |
| 11 | /* |
| 12 | * FILE PURPOSE: Local Power Sleep Controller definitions |
| 13 | * |
| 14 | * FILE NAME: psc_defs.h |
| 15 | * |
| 16 | * DESCRIPTION: Provides local definitions for the power saver controller |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | /* Register offsets */ |
| 21 | #define PSC_REG_PTCMD 0x120 |
| 22 | #define PSC_REG_PSTAT 0x128 |
| 23 | #define PSC_REG_PDSTAT(x) (0x200 + (4 * (x))) |
| 24 | #define PSC_REG_PDCTL(x) (0x300 + (4 * (x))) |
| 25 | #define PSC_REG_MDCFG(x) (0x600 + (4 * (x))) |
| 26 | #define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) |
| 27 | #define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) |
| 28 | |
Nishanth Menon | 40d581a | 2016-03-15 10:25:51 -0500 | [diff] [blame] | 29 | static inline u32 _boot_bit_mask(u32 x, u32 y) |
| 30 | { |
| 31 | u32 val = (1 << (x - y + 1)) - 1; |
| 32 | return val << y; |
| 33 | } |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 34 | |
Nishanth Menon | 5a25646 | 2016-03-15 10:25:52 -0500 | [diff] [blame] | 35 | static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y) |
| 36 | { |
| 37 | u32 val = z & _boot_bit_mask(x, y); |
| 38 | return val >> y; |
| 39 | } |
| 40 | |
Nishanth Menon | 7bb2672 | 2016-03-15 10:25:53 -0500 | [diff] [blame] | 41 | static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y) |
| 42 | { |
| 43 | u32 mask = _boot_bit_mask(x, y); |
| 44 | |
| 45 | return (z & ~mask) | ((f << y) & mask); |
| 46 | } |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 47 | |
| 48 | /* PDCTL */ |
Nishanth Menon | 7bb2672 | 2016-03-15 10:25:53 -0500 | [diff] [blame] | 49 | #define PSC_REG_PDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 0, 0) |
| 50 | #define PSC_REG_PDCTL_SET_PDMODE(x, y) boot_set_bitfield((x), (y), 15, 12) |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 51 | |
| 52 | /* PDSTAT */ |
Nishanth Menon | 5a25646 | 2016-03-15 10:25:52 -0500 | [diff] [blame] | 53 | #define PSC_REG_PDSTAT_GET_STATE(x) boot_read_bitfield((x), 4, 0) |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 54 | |
| 55 | /* MDCFG */ |
Nishanth Menon | 5a25646 | 2016-03-15 10:25:52 -0500 | [diff] [blame] | 56 | #define PSC_REG_MDCFG_GET_PD(x) boot_read_bitfield((x), 20, 16) |
| 57 | #define PSC_REG_MDCFG_GET_RESET_ISO(x) boot_read_bitfield((x), 14, 14) |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 58 | |
| 59 | /* MDCTL */ |
Nishanth Menon | 7bb2672 | 2016-03-15 10:25:53 -0500 | [diff] [blame] | 60 | #define PSC_REG_MDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 4, 0) |
| 61 | #define PSC_REG_MDCTL_SET_LRSTZ(x, y) boot_set_bitfield((x), (y), 8, 8) |
Nishanth Menon | 5a25646 | 2016-03-15 10:25:52 -0500 | [diff] [blame] | 62 | #define PSC_REG_MDCTL_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8) |
Nishanth Menon | 7bb2672 | 2016-03-15 10:25:53 -0500 | [diff] [blame] | 63 | #define PSC_REG_MDCTL_SET_RESET_ISO(x, y) boot_set_bitfield((x), (y), \ |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 64 | 12, 12) |
| 65 | |
| 66 | /* MDSTAT */ |
Nishanth Menon | 5a25646 | 2016-03-15 10:25:52 -0500 | [diff] [blame] | 67 | #define PSC_REG_MDSTAT_GET_STATUS(x) boot_read_bitfield((x), 5, 0) |
| 68 | #define PSC_REG_MDSTAT_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8) |
| 69 | #define PSC_REG_MDSTAT_GET_LRSTDONE(x) boot_read_bitfield((x), 9, 9) |
| 70 | #define PSC_REG_MDSTAT_GET_MRSTZ(x) boot_read_bitfield((x), 10, 10) |
| 71 | #define PSC_REG_MDSTAT_GET_MRSTDONE(x) boot_read_bitfield((x), 11, 11) |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 72 | |
| 73 | /* PDCTL states */ |
| 74 | #define PSC_REG_VAL_PDCTL_NEXT_ON 1 |
| 75 | #define PSC_REG_VAL_PDCTL_NEXT_OFF 0 |
| 76 | |
| 77 | #define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0 |
| 78 | |
| 79 | /* MDCTL states */ |
| 80 | #define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0 |
| 81 | #define PSC_REG_VAL_MDCTL_NEXT_OFF 2 |
| 82 | #define PSC_REG_VAL_MDCTL_NEXT_ON 3 |
| 83 | |
| 84 | /* MDSTAT states */ |
| 85 | #define PSC_REG_VAL_MDSTAT_STATE_ON 3 |
| 86 | #define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24 |
| 87 | #define PSC_REG_VAL_MDSTAT_STATE_OFF 2 |
| 88 | #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20 |
| 89 | #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21 |
| 90 | #define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22 |
| 91 | |
| 92 | /* |
| 93 | * Timeout limit on checking PTSTAT. This is the number of times the |
| 94 | * wait function will be called before giving up. |
| 95 | */ |
Jean-Jacques Hiblot | 15a60a2 | 2019-09-11 11:33:54 +0200 | [diff] [blame] | 96 | #define PSC_PTSTAT_TIMEOUT_LIMIT 100000 |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 97 | |
| 98 | u32 psc_get_domain_num(u32 mod_num); |
| 99 | int psc_enable_module(u32 mod_num); |
| 100 | int psc_disable_module(u32 mod_num); |
| 101 | int psc_disable_domain(u32 domain_num); |
Nishanth Menon | 06a1087 | 2016-02-25 12:53:44 -0600 | [diff] [blame] | 102 | int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks); |
| 103 | int psc_module_release_from_reset(u32 mod_num); |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 104 | |
| 105 | #endif /* _PSC_DEFS_H_ */ |