Thierry Reding | 7cef2b2 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (c) 2019 NVIDIA Corporation. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _TEGRA_CBOOT_H_ |
| 7 | #define _TEGRA_CBOOT_H_ |
| 8 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 9 | #include <linux/errno.h> |
| 10 | #include <linux/types.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 11 | #include <net.h> |
| 12 | |
Thierry Reding | 7cef2b2 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 13 | #ifdef CONFIG_ARM64 |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 14 | |
Thierry Reding | 7cef2b2 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 15 | extern unsigned long cboot_boot_x0; |
| 16 | |
| 17 | void cboot_save_boot_params(unsigned long x0, unsigned long x1, |
| 18 | unsigned long x2, unsigned long x3); |
| 19 | int cboot_dram_init(void); |
| 20 | int cboot_dram_init_banksize(void); |
| 21 | ulong cboot_get_usable_ram_top(ulong total_size); |
Thierry Reding | 37bb829 | 2019-04-15 11:32:30 +0200 | [diff] [blame] | 22 | int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]); |
Thierry Reding | 7cef2b2 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 23 | #else |
| 24 | static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1, |
| 25 | unsigned long x2, unsigned long x3) |
| 26 | { |
| 27 | } |
| 28 | |
| 29 | static inline int cboot_dram_init(void) |
| 30 | { |
| 31 | return -ENOSYS; |
| 32 | } |
| 33 | |
| 34 | static inline int cboot_dram_init_banksize(void) |
| 35 | { |
| 36 | return -ENOSYS; |
| 37 | } |
| 38 | |
| 39 | static inline ulong cboot_get_usable_ram_top(ulong total_size) |
| 40 | { |
| 41 | return 0; |
| 42 | } |
Thierry Reding | 37bb829 | 2019-04-15 11:32:30 +0200 | [diff] [blame] | 43 | |
| 44 | static inline int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]) |
| 45 | { |
| 46 | return -ENOSYS; |
| 47 | } |
Thierry Reding | 7cef2b2 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 48 | #endif |
| 49 | |
| 50 | #endif |