blob: 64bb0b6ee0bd45bdc1ad2b171bd6837b44de099c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chris Zankel1387dab2016-08-10 18:36:44 +03002/*
3 * (C) Copyright 2008 - 2013 Tensilica Inc.
4 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
Chris Zankel1387dab2016-08-10 18:36:44 +03005 */
6
7/*
8 * CPU specific code
9 */
10
11#include <common.h>
12#include <command.h>
13#include <linux/stringify.h>
14#include <asm/global_data.h>
15#include <asm/cache.h>
16#include <asm/string.h>
17#include <asm/misc.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21gd_t *gd __attribute__((section(".data")));
22
23#if defined(CONFIG_DISPLAY_CPUINFO)
24/*
25 * Print information about the CPU.
26 */
27
28int print_cpuinfo(void)
29{
30 char buf[120], mhz[8];
31 uint32_t id0, id1;
32
33 asm volatile ("rsr %0, 176\n"
34 "rsr %1, 208\n"
35 : "=r"(id0), "=r"(id1));
36
37 sprintf(buf, "CPU: Xtensa %s (id: %08x:%08x) at %s MHz\n",
38 XCHAL_CORE_ID, id0, id1, strmhz(mhz, gd->cpu_clk));
39 puts(buf);
40 return 0;
41}
42#endif
43
44int arch_cpu_init(void)
45{
46 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
47 return 0;
48}
Simon Glassd35f3382017-04-06 12:47:05 -060049
50int dram_init(void)
51{
52 return 0;
53}