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git01.mediatek.com / filogic / uboot / ccede76687afca59c76b56e9e66910ed618503a8 / . / board / funkwerk / vovpn-gw / vovpn-gw.c
blob: 8c4abdd370668dd9cb50fcc85e4b7032fbb58418 [file] [log] [blame]
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]1/*
2 * (C) Copyright 2004
3 * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
4 *
5 * Support for the Elmeg VoVPN Gateway Module
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <ioports.h>
25#include <mpc8260.h>
26#include <asm/m8260_pci.h>
27#include <miiphy.h>
28
29#include "m88e6060.h"
30
31/*
32 * I/O Port configuration table
33 *
34 * if conf is 1, then that port pin will be configured at boot time
35 * according to the five values podr/pdir/ppar/psor/pdat for that entry
36 */
37
38const iop_conf_t iop_conf_tab[4][32] = {
39 /* Port A configuration */
40 { /* conf ppar psor pdir podr pdat */
41 /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */
42 /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */
43 /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */
44 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */
45 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */
46 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */
47 /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
48 /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
49 /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
50 /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
51 /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
52 /* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */
53 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */
54 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */
55 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */
56 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */
57 /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */
58 /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */
59 /* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */
60 /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */
61 /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */
62 /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */
63 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
64 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
65 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
66 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
67 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
68 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
69 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
70 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
71 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
72 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */
73 },
74
75 /* Port B configuration */
76 { /* conf ppar psor pdir podr pdat */
77 /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */
78 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */
79 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */
80 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */
81 /* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */
82 /* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */
83 /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */
84 /* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */
85 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */
86 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */
87 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */
88 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */
89 /* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */
90 /* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */
91 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
92 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
93 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
94 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
95 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
96 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
97 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
98 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
99 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
100 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
101 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
102 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
103 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
104 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
105 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
106 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
107 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
108 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
109 },
110
111 /* Port C */
112 { /* conf ppar psor pdir podr pdat */
113 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
114 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
115 /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */
116 /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */
117 /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */
118 /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */
119 /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */
120 /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */
121 /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */
122 /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */
123 /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */
124 /* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */
125 /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */
126 /* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */
127 /* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */
128 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */
129 /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */
130 /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */
131 /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */
132 /* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */
133 /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */
134 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */
135 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */
136 /* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */
137 /* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */
138 /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */
139 /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
140 /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
141 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
142 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
143 /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */
144 /* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */
145 },
146
147 /* Port D */
148 { /* conf ppar psor pdir podr pdat */
149 /* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */
150 /* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */
151 /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */
152 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
153 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
154 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
155 /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */
156 /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */
157 /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */
158 /* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */
159 /* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */
160 /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
161 /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */
162 /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */
163 /* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */
164 /* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */
165 /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */
166 /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */
167 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
168 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
169 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
170 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
171 /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
172 /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
173 /* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */
174 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
175 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
176 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
177 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
178 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
179 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
180 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
181 }
182};
183
184void reset_phy (void)
185{
186 volatile ioport_t *iop;
Jon Loeliger96892a92007-07-09 18:31:28 -0500[diff] [blame]187#if defined(CONFIG_CMD_NET)
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]188 int i;
189 unsigned short val;
190#endif
191
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]192 iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]193
194 /* Reset the PHY */
195 iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */
Jon Loeliger96892a92007-07-09 18:31:28 -0500[diff] [blame]196#if defined(CONFIG_CMD_NET)
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]197 udelay(20000);
198 iop->pdat |= 0x00080000;
199 for (i=0; i<100; i++) {
200 udelay(20000);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]201 if (bb_miiphy_read("FCC1 ETHERNET", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) {
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]202 break;
203 }
204 }
205 /* initialize switch */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]206 m88e6060_initialize( CONFIG_SYS_PHY_ADDR );
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]207#endif
208}
209
210static unsigned long UPMATable[] = {
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200[diff] [blame]211 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */
212 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */
213 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */
214 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */
215 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */
216 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
217 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */
218 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
219 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */
220 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */
221 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
222 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
223 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */
224 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
225 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
226 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]227};
228
229int board_early_init_f (void)
230{
231 volatile immap_t *immap;
232 volatile memctl8260_t *memctl;
233 volatile unsigned char *dummy;
234 int i;
235
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]236 immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]237 memctl = &immap->im_memctl;
238
239#if 0
240 /* CS2-5 - DSP via UPMA */
241 dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
242 memctl->memc_mar = 0;
243 memctl->memc_mamr = MxMR_OP_WARR;
244 for (i = 0; i < 64; i++) {
245 memctl->memc_mdr = UPMATable[i];
246 *dummy = 0;
247 }
248 memctl->memc_mamr = 0x00044440;
249#else
250 /* CS7 - DPRAM via UPMA */
251 dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
252 memctl->memc_mar = 0;
253 memctl->memc_mamr = MxMR_OP_WARR;
254 for (i = 0; i < 64; i++) {
255 memctl->memc_mdr = UPMATable[i];
256 *dummy = 0;
257 }
258 memctl->memc_mamr = 0x00044440;
259#endif
260 return 0;
261}
262
263int misc_init_r (void)
264{
265 volatile ioport_t *iop;
266 unsigned char temp;
267#if 0
268 /* DUMP UPMA RAM */
269 volatile immap_t *immap;
270 volatile memctl8260_t *memctl;
271 volatile unsigned char *dummy;
272 unsigned char c;
273 int i;
274
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]275 immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]276 memctl = &immap->im_memctl;
277
278
279 dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
280 memctl->memc_mar = 0;
281 memctl->memc_mamr = MxMR_OP_RARR;
282 for (i = 0; i < 64; i++) {
283 c = *dummy;
284 printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
285 memctl->memc_mamr,
286 memctl->memc_mar,
287 memctl->memc_mdr );
288 }
289 memctl->memc_mamr = 0x00044440;
290#endif
291 /* enable buffers (DSP, DPRAM) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]292 iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]293 iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */
294
295 /* destroy DPRAM magic */
296 *(volatile unsigned char *)0xf0500000 = 0x00;
297
298 /* clear any pending DPRAM irq */
299 temp = *(volatile unsigned char *)0xf05003ff;
300
301 /* write module-id into DPRAM */
302 *(volatile unsigned char *)0xf0500201 = 0x50;
303
304 return 0;
305}
306
307#if defined(CONFIG_HAVE_OWN_RESET)
308int
309do_reset (void *cmdtp, int flag, int argc, char *argv[])
310{
311 volatile ioport_t *iop;
312
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]313 iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2);
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]314 iop->pdat |= 0x00002000; /* PC18 = HW_RESET */
315 return 1;
316}
317#endif /* CONFIG_HAVE_OWN_RESET */
318
319#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
320
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]321phys_size_t initdram (int board_type)
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]322{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]323#ifndef CONFIG_SYS_RAMBOOT
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]324 volatile immap_t *immap;
325 volatile memctl8260_t *memctl;
326 volatile uchar *ramaddr;
327 int i;
328 uchar c;
329
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]330 immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]331 memctl = &immap->im_memctl;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]332 ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]333 c = 0xff;
334
335 immap->im_siu_conf.sc_ppc_acr = 0x02;
336 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
337 immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
338 immap->im_siu_conf.sc_tescr1 = 0x00000000;
339 immap->im_siu_conf.sc_tescr2 = 0x00000000;
340
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]341 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
342 memctl->memc_psrt = CONFIG_SYS_PSRT;
343 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
344 memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_BR1_PRELIM;
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]345
346 /* Precharge all banks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]347 memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]348 *ramaddr = c;
349
350 /* CBR refresh */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]351 memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]352 for (i = 0; i < 8; i++)
353 *ramaddr = c;
354
355 /* Mode Register write */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]356 memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]357 *ramaddr = c;
358
359 /* Refresh enable */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]360 memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]361 *ramaddr = c;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]362#endif /* CONFIG_SYS_RAMBOOT */
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]363
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]364 return (CONFIG_SYS_SDRAM_SIZE);
wdenkc28149c2005-05-30 23:55:42 +0000[diff] [blame]365}
366
367int checkboard (void)
368{
369#ifdef CONFIG_CLKIN_66MHz
370 puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
371#else
372 puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
373#endif
374 return 0;
375}