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git01.mediatek.com / filogic / uboot / cce3e75fa6a3779e5f7be89024d892d6e770cfe1 / . / arch / arm / include / asm / arch-keystone / emac_defs.h
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Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400[diff] [blame]1/*
2 * emac definitions for keystone2 devices
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef _EMAC_DEFS_H_
11#define _EMAC_DEFS_H_
12
13#include <asm/arch/hardware.h>
14#include <asm/io.h>
15
16#define DEVICE_REG32_R(a) readl(a)
17#define DEVICE_REG32_W(a, v) writel(v, a)
18
19#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
20#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
21#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
22
23#define KEYSTONE2_EMAC_GIG_ENABLE
24
25#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
26
27#ifdef CONFIG_SOC_K2HK
28/* MDIO module input frequency */
29#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
30/* MDIO clock output frequency */
31#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
32#endif
33
34/* MII Status Register */
35#define MII_STATUS_REG 1
36#define MII_STATUS_LINK_MASK (0x4)
37
38/* Marvell 88E1111 PHY ID */
39#define PHY_MARVELL_88E1111 (0x01410cc0)
40
41#define MDIO_CONTROL_IDLE (0x80000000)
42#define MDIO_CONTROL_ENABLE (0x40000000)
43#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
44#define MDIO_CONTROL_FAULT (0x80000)
45#define MDIO_USERACCESS0_GO (0x80000000)
46#define MDIO_USERACCESS0_WRITE_READ (0x0)
47#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
48#define MDIO_USERACCESS0_ACK (0x20000000)
49
50#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
51#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
52#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
53#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
54#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
55
56#define EMAC_MIN_ETHERNET_PKT_SIZE 60
57
58struct mac_sl_cfg {
59 u_int32_t max_rx_len; /* Maximum receive packet length. */
60 u_int32_t ctl; /* Control bitfield */
61};
62
63/*
64 * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
65 */
66#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
67#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
68#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
69#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
70#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17)
71#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
72#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
73#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
74#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10)
75#define GMACSL_ENABLE_GIG_MODE (1 << 7)
76#define GMACSL_TX_ENABLE_PACE (1 << 6)
77#define GMACSL_ENABLE (1 << 5)
78#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
79#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
80#define GMACSL_ENABLE_LOOPBACK (1 << 1)
81#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
82
83/*
84 * DEFINTITION: function return values
85 */
86#define GMACSL_RET_OK 0
87#define GMACSL_RET_INVALID_PORT -1
88#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
89#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
90#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
91
92/* Register offsets */
93#define CPGMACSL_REG_ID 0x00
94#define CPGMACSL_REG_CTL 0x04
95#define CPGMACSL_REG_STATUS 0x08
96#define CPGMACSL_REG_RESET 0x0c
97#define CPGMACSL_REG_MAXLEN 0x10
98#define CPGMACSL_REG_BOFF 0x14
99#define CPGMACSL_REG_RX_PAUSE 0x18
100#define CPGMACSL_REG_TX_PAURSE 0x1c
101#define CPGMACSL_REG_EM_CTL 0x20
102#define CPGMACSL_REG_PRI 0x24
103
104/* Soft reset register values */
105#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
106#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
107
108/* Maxlen register values */
109#define CPGMAC_REG_MAXLEN_LEN 0x3fff
110
111/* Control bitfields */
112#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5)
113#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4)
114#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3)
115#define CPSW_CTL_P0_ENABLE (1 << 2)
116#define CPSW_CTL_VLAN_AWARE (1 << 1)
117#define CPSW_CTL_FIFO_LOOPBACK (1 << 0)
118
119#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */
120#define DEVICE_CPSW_BASE (0x02090800)
121#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
122#define SWITCH_MAX_PKT_SIZE 9000
123
124/* Register offsets */
125#define CPSW_REG_CTL 0x004
126#define CPSW_REG_STAT_PORT_EN 0x00c
127#define CPSW_REG_MAXLEN 0x040
128#define CPSW_REG_ALE_CONTROL 0x608
129#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4)
130
131/* Register values */
132#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
133#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
134#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
135#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
136
137#define SGMII_REG_STATUS_LOCK BIT(4)
138#define SGMII_REG_STATUS_LINK BIT(0)
139#define SGMII_REG_STATUS_AUTONEG BIT(2)
140#define SGMII_REG_CONTROL_AUTONEG BIT(0)
141#define SGMII_REG_CONTROL_MASTER BIT(5)
142#define SGMII_REG_MR_ADV_ENABLE BIT(0)
143#define SGMII_REG_MR_ADV_LINK BIT(15)
144#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
145#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
146
147#define SGMII_LINK_MAC_MAC_AUTONEG 0
148#define SGMII_LINK_MAC_PHY 1
149#define SGMII_LINK_MAC_MAC_FORCED 2
150#define SGMII_LINK_MAC_FIBER 3
151#define SGMII_LINK_MAC_PHY_FORCED 4
152
153#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100
154#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \
155 KS2_PASS_BASE + 0x00090200, \
156 KS2_PASS_BASE + 0x00090400, \
157 KS2_PASS_BASE + 0x00090500}
158
159#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
160
161/*
162 * SGMII registers
163 */
164#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
165#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
166#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
167#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
168#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
169#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
170#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
171#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
172#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
173
174#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
175#define DEVICE_N_GMACSL_PORTS 4
176#define DEVICE_EMACSL_RESET_POLL_COUNT 100
177
178#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
179
180#ifdef CONFIG_SOC_K2HK
181#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606
182#endif
183
184#define hw_config_streaming_switch() \
185 DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, \
186 DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI);
187
188/* EMAC MDIO Registers Structure */
189struct mdio_regs {
190 dv_reg version;
191 dv_reg control;
192 dv_reg alive;
193 dv_reg link;
194 dv_reg linkintraw;
195 dv_reg linkintmasked;
196 u_int8_t rsvd0[8];
197 dv_reg userintraw;
198 dv_reg userintmasked;
199 dv_reg userintmaskset;
200 dv_reg userintmaskclear;
201 u_int8_t rsvd1[80];
202 dv_reg useraccess0;
203 dv_reg userphysel0;
204 dv_reg useraccess1;
205 dv_reg userphysel1;
206};
207
208/* Ethernet MAC Registers Structure */
209struct emac_regs {
210 dv_reg idver;
211 dv_reg maccontrol;
212 dv_reg macstatus;
213 dv_reg soft_reset;
214 dv_reg rx_maxlen;
215 u32 rsvd0;
216 dv_reg rx_pause;
217 dv_reg tx_pause;
218 dv_reg emcontrol;
219 dv_reg pri_map;
220 u32 rsvd1[6];
221};
222
223#define SGMII_ACCESS(port, reg) \
224 *((volatile unsigned int *)(sgmiis[port] + reg))
225
226struct eth_priv_t {
227 char int_name[32];
228 int rx_flow;
229 int phy_addr;
230 int slave_port;
231 int sgmii_link_type;
232};
233
234extern struct eth_priv_t eth_priv_cfg[];
235
236int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
237void sgmii_serdes_setup_156p25mhz(void);
238void sgmii_serdes_shutdown(void);
239
240#endif /* _EMAC_DEFS_H_ */