blob: a77521479280c1534ca0fc667b05ba69f714c63d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefano Babic771bfd12012-02-22 00:24:39 +00002/*
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * Terry Lv <r65388@freescale.com>
Stefano Babic771bfd12012-02-22 00:24:39 +00005 */
6
Simon Glass602cedc2017-07-29 11:35:08 -06007#include <common.h>
Stefano Babic771bfd12012-02-22 00:24:39 +00008#include <ahci.h>
Simon Glass63334482019-11-14 12:57:39 -07009#include <cpu_func.h>
Simon Glass0067b872017-07-29 11:35:16 -060010#include <dm.h>
11#include <dwc_ahsata.h>
Stefano Babic771bfd12012-02-22 00:24:39 +000012#include <fis.h>
Simon Glass602cedc2017-07-29 11:35:08 -060013#include <libata.h>
Stefano Babic771bfd12012-02-22 00:24:39 +000014#include <malloc.h>
Simon Glassf89b2502017-07-29 11:35:12 -060015#include <memalign.h>
Simon Glass602cedc2017-07-29 11:35:08 -060016#include <sata.h>
Stefano Babic771bfd12012-02-22 00:24:39 +000017#include <asm/io.h>
Stefano Babic771bfd12012-02-22 00:24:39 +000018#include <asm/arch/clock.h>
Tim Harveye9d13472014-05-07 22:23:35 -070019#include <asm/arch/sys_proto.h>
Soeren Moch5569bbd2019-03-01 13:10:59 +010020#include <asm/mach-imx/sata.h>
Simon Glass602cedc2017-07-29 11:35:08 -060021#include <linux/bitops.h>
22#include <linux/ctype.h>
23#include <linux/errno.h>
Simon Glass7b2a6292017-07-29 11:35:09 -060024#include "dwc_ahsata_priv.h"
Stefano Babic771bfd12012-02-22 00:24:39 +000025
26struct sata_port_regs {
27 u32 clb;
28 u32 clbu;
29 u32 fb;
30 u32 fbu;
31 u32 is;
32 u32 ie;
33 u32 cmd;
34 u32 res1[1];
35 u32 tfd;
36 u32 sig;
37 u32 ssts;
38 u32 sctl;
39 u32 serr;
40 u32 sact;
41 u32 ci;
42 u32 sntf;
43 u32 res2[1];
44 u32 dmacr;
45 u32 res3[1];
46 u32 phycr;
47 u32 physr;
48};
49
50struct sata_host_regs {
51 u32 cap;
52 u32 ghc;
53 u32 is;
54 u32 pi;
55 u32 vs;
56 u32 ccc_ctl;
57 u32 ccc_ports;
58 u32 res1[2];
59 u32 cap2;
60 u32 res2[30];
61 u32 bistafr;
62 u32 bistcr;
63 u32 bistfctr;
64 u32 bistsr;
65 u32 bistdecr;
66 u32 res3[2];
67 u32 oobr;
68 u32 res4[8];
69 u32 timer1ms;
70 u32 res5[1];
71 u32 gparam1r;
72 u32 gparam2r;
73 u32 pparamr;
74 u32 testr;
75 u32 versionr;
76 u32 idr;
77};
78
79#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
80#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
81
82#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
83
Tang Yuantian3f262d02015-07-09 14:37:30 +080084static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
Stefano Babic771bfd12012-02-22 00:24:39 +000085{
86 return base + 0x100 + (port * 0x80);
87}
88
89static int waiting_for_cmd_completed(u8 *offset,
90 int timeout_msec,
91 u32 sign)
92{
93 int i;
94 u32 status;
95
96 for (i = 0;
97 ((status = readl(offset)) & sign) && i < timeout_msec;
98 ++i)
99 mdelay(1);
100
101 return (i < timeout_msec) ? 0 : -1;
102}
103
Simon Glassb1f7f582017-07-29 11:35:04 -0600104static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
Stefano Babic771bfd12012-02-22 00:24:39 +0000105{
Simon Glassd30e76c2017-07-29 11:35:05 -0600106 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
Stefano Babic771bfd12012-02-22 00:24:39 +0000107
Simon Glass96f2af42017-07-29 11:35:07 -0600108 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
109 writel(0x02060b14, &host_mmio->oobr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000110
111 return 0;
112}
113
Simon Glassb1f7f582017-07-29 11:35:04 -0600114static int ahci_host_init(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000115{
116 u32 tmp, cap_save, num_ports;
117 int i, j, timeout = 1000;
118 struct sata_port_regs *port_mmio = NULL;
Simon Glassd30e76c2017-07-29 11:35:05 -0600119 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
Stefano Babic771bfd12012-02-22 00:24:39 +0000120 int clk = mxc_get_clock(MXC_SATA_CLK);
121
Simon Glass96f2af42017-07-29 11:35:07 -0600122 cap_save = readl(&host_mmio->cap);
Stefano Babic771bfd12012-02-22 00:24:39 +0000123 cap_save |= SATA_HOST_CAP_SSS;
124
125 /* global controller reset */
Simon Glass96f2af42017-07-29 11:35:07 -0600126 tmp = readl(&host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000127 if ((tmp & SATA_HOST_GHC_HR) == 0)
Simon Glass96f2af42017-07-29 11:35:07 -0600128 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000129
Simon Glass96f2af42017-07-29 11:35:07 -0600130 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
Stefano Babic771bfd12012-02-22 00:24:39 +0000131 ;
132
133 if (timeout <= 0) {
134 debug("controller reset failed (0x%x)\n", tmp);
135 return -1;
136 }
137
138 /* Set timer 1ms */
Simon Glass96f2af42017-07-29 11:35:07 -0600139 writel(clk / 1000, &host_mmio->timer1ms);
Stefano Babic771bfd12012-02-22 00:24:39 +0000140
Simon Glassb1f7f582017-07-29 11:35:04 -0600141 ahci_setup_oobr(uc_priv, 0);
Stefano Babic771bfd12012-02-22 00:24:39 +0000142
Simon Glass96f2af42017-07-29 11:35:07 -0600143 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
144 writel(cap_save, &host_mmio->cap);
Stefano Babic771bfd12012-02-22 00:24:39 +0000145 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
Simon Glass96f2af42017-07-29 11:35:07 -0600146 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
Stefano Babic771bfd12012-02-22 00:24:39 +0000147
148 /*
149 * Determine which Ports are implemented by the DWC_ahsata,
150 * by reading the PI register. This bit map value aids the
151 * software to determine how many Ports are available and
152 * which Port registers need to be initialized.
153 */
Simon Glass96f2af42017-07-29 11:35:07 -0600154 uc_priv->cap = readl(&host_mmio->cap);
155 uc_priv->port_map = readl(&host_mmio->pi);
Stefano Babic771bfd12012-02-22 00:24:39 +0000156
157 /* Determine how many command slots the HBA supports */
Simon Glassb1f7f582017-07-29 11:35:04 -0600158 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
Stefano Babic771bfd12012-02-22 00:24:39 +0000159
160 debug("cap 0x%x port_map 0x%x n_ports %d\n",
Simon Glassb1f7f582017-07-29 11:35:04 -0600161 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
Stefano Babic771bfd12012-02-22 00:24:39 +0000162
Simon Glassb1f7f582017-07-29 11:35:04 -0600163 for (i = 0; i < uc_priv->n_ports; i++) {
164 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
Simon Glassd30e76c2017-07-29 11:35:05 -0600165 port_mmio = uc_priv->port[i].port_mmio;
Stefano Babic771bfd12012-02-22 00:24:39 +0000166
167 /* Ensure that the DWC_ahsata is in idle state */
Simon Glass96f2af42017-07-29 11:35:07 -0600168 tmp = readl(&port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000169
170 /*
171 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
172 * are all cleared, the Port is in an idle state.
173 */
174 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
175 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
176
177 /*
178 * System software places a Port into the idle state by
179 * clearing P#CMD.ST and waiting for P#CMD.CR to return
180 * 0 when read.
181 */
182 tmp &= ~SATA_PORT_CMD_ST;
Simon Glass96f2af42017-07-29 11:35:07 -0600183 writel_with_flush(tmp, &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000184
185 /*
186 * spec says 500 msecs for each bit, so
187 * this is slightly incorrect.
188 */
189 mdelay(500);
190
191 timeout = 1000;
Simon Glass96f2af42017-07-29 11:35:07 -0600192 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
Stefano Babic771bfd12012-02-22 00:24:39 +0000193 && --timeout)
194 ;
195
196 if (timeout <= 0) {
197 debug("port reset failed (0x%x)\n", tmp);
198 return -1;
199 }
200 }
201
202 /* Spin-up device */
Simon Glass96f2af42017-07-29 11:35:07 -0600203 tmp = readl(&port_mmio->cmd);
204 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000205
206 /* Wait for spin-up to finish */
207 timeout = 1000;
Simon Glass96f2af42017-07-29 11:35:07 -0600208 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
Stefano Babic771bfd12012-02-22 00:24:39 +0000209 && --timeout)
210 ;
211 if (timeout <= 0) {
212 debug("Spin-Up can't finish!\n");
213 return -1;
214 }
215
216 for (j = 0; j < 100; ++j) {
217 mdelay(10);
Simon Glass96f2af42017-07-29 11:35:07 -0600218 tmp = readl(&port_mmio->ssts);
Stefano Babic771bfd12012-02-22 00:24:39 +0000219 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
220 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
221 break;
222 }
223
224 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
225 timeout = 1000;
Simon Glass96f2af42017-07-29 11:35:07 -0600226 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X)
Stefano Babic771bfd12012-02-22 00:24:39 +0000227 && --timeout)
228 ;
229 if (timeout <= 0) {
230 debug("Can't find DIAG_X set!\n");
231 return -1;
232 }
233
234 /*
235 * For each implemented Port, clear the P#SERR
236 * register, by writing ones to each implemented\
237 * bit location.
238 */
Simon Glass96f2af42017-07-29 11:35:07 -0600239 tmp = readl(&port_mmio->serr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000240 debug("P#SERR 0x%x\n",
241 tmp);
Simon Glass96f2af42017-07-29 11:35:07 -0600242 writel(tmp, &port_mmio->serr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000243
244 /* Ack any pending irq events for this port */
Simon Glass96f2af42017-07-29 11:35:07 -0600245 tmp = readl(&host_mmio->is);
Stefano Babic771bfd12012-02-22 00:24:39 +0000246 debug("IS 0x%x\n", tmp);
247 if (tmp)
Simon Glass96f2af42017-07-29 11:35:07 -0600248 writel(tmp, &host_mmio->is);
Stefano Babic771bfd12012-02-22 00:24:39 +0000249
Simon Glass96f2af42017-07-29 11:35:07 -0600250 writel(1 << i, &host_mmio->is);
Stefano Babic771bfd12012-02-22 00:24:39 +0000251
252 /* set irq mask (enables interrupts) */
Simon Glass96f2af42017-07-29 11:35:07 -0600253 writel(DEF_PORT_IRQ, &port_mmio->ie);
Stefano Babic771bfd12012-02-22 00:24:39 +0000254
255 /* register linkup ports */
Simon Glass96f2af42017-07-29 11:35:07 -0600256 tmp = readl(&port_mmio->ssts);
Stefano Babic771bfd12012-02-22 00:24:39 +0000257 debug("Port %d status: 0x%x\n", i, tmp);
258 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
Simon Glassb1f7f582017-07-29 11:35:04 -0600259 uc_priv->link_port_map |= (0x01 << i);
Stefano Babic771bfd12012-02-22 00:24:39 +0000260 }
261
Simon Glass96f2af42017-07-29 11:35:07 -0600262 tmp = readl(&host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000263 debug("GHC 0x%x\n", tmp);
Simon Glass96f2af42017-07-29 11:35:07 -0600264 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
265 tmp = readl(&host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000266 debug("GHC 0x%x\n", tmp);
267
268 return 0;
269}
270
Simon Glassb1f7f582017-07-29 11:35:04 -0600271static void ahci_print_info(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000272{
Simon Glassd30e76c2017-07-29 11:35:05 -0600273 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
Stefano Babic771bfd12012-02-22 00:24:39 +0000274 u32 vers, cap, impl, speed;
275 const char *speed_s;
276 const char *scc_s;
277
Simon Glass96f2af42017-07-29 11:35:07 -0600278 vers = readl(&host_mmio->vs);
Simon Glassb1f7f582017-07-29 11:35:04 -0600279 cap = uc_priv->cap;
280 impl = uc_priv->port_map;
Stefano Babic771bfd12012-02-22 00:24:39 +0000281
282 speed = (cap & SATA_HOST_CAP_ISS_MASK)
283 >> SATA_HOST_CAP_ISS_OFFSET;
284 if (speed == 1)
285 speed_s = "1.5";
286 else if (speed == 2)
287 speed_s = "3";
288 else
289 speed_s = "?";
290
291 scc_s = "SATA";
292
293 printf("AHCI %02x%02x.%02x%02x "
294 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
295 (vers >> 24) & 0xff,
296 (vers >> 16) & 0xff,
297 (vers >> 8) & 0xff,
298 vers & 0xff,
299 ((cap >> 8) & 0x1f) + 1,
300 (cap & 0x1f) + 1,
301 speed_s,
302 impl,
303 scc_s);
304
305 printf("flags: "
306 "%s%s%s%s%s%s"
307 "%s%s%s%s%s%s%s\n",
308 cap & (1 << 31) ? "64bit " : "",
309 cap & (1 << 30) ? "ncq " : "",
310 cap & (1 << 28) ? "ilck " : "",
311 cap & (1 << 27) ? "stag " : "",
312 cap & (1 << 26) ? "pm " : "",
313 cap & (1 << 25) ? "led " : "",
314 cap & (1 << 24) ? "clo " : "",
315 cap & (1 << 19) ? "nz " : "",
316 cap & (1 << 18) ? "only " : "",
317 cap & (1 << 17) ? "pmp " : "",
318 cap & (1 << 15) ? "pio " : "",
319 cap & (1 << 14) ? "slum " : "",
320 cap & (1 << 13) ? "part " : "");
321}
322
Simon Glassb1f7f582017-07-29 11:35:04 -0600323static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
324 unsigned char *buf, int buf_len)
Stefano Babic771bfd12012-02-22 00:24:39 +0000325{
Simon Glass96f2af42017-07-29 11:35:07 -0600326 struct ahci_ioports *pp = &uc_priv->port[port];
Stefano Babic771bfd12012-02-22 00:24:39 +0000327 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
328 u32 sg_count, max_bytes;
329 int i;
330
331 max_bytes = MAX_DATA_BYTES_PER_SG;
332 sg_count = ((buf_len - 1) / max_bytes) + 1;
333 if (sg_count > AHCI_MAX_SG) {
334 printf("Error:Too much sg!\n");
335 return -1;
336 }
337
338 for (i = 0; i < sg_count; i++) {
339 ahci_sg->addr =
340 cpu_to_le32((u32)buf + i * max_bytes);
341 ahci_sg->addr_hi = 0;
342 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
343 (buf_len < max_bytes
344 ? (buf_len - 1)
345 : (max_bytes - 1)));
346 ahci_sg++;
347 buf_len -= max_bytes;
348 }
349
350 return sg_count;
351}
352
353static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
354{
355 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
356 AHCI_CMD_SLOT_SZ * cmd_slot);
357
358 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
359 cmd_hdr->opts = cpu_to_le32(opts);
360 cmd_hdr->status = 0;
Tang Yuantian3f262d02015-07-09 14:37:30 +0800361 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
362#ifdef CONFIG_PHYS_64BIT
363 pp->cmd_slot->tbl_addr_hi =
364 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
365#endif
Stefano Babic771bfd12012-02-22 00:24:39 +0000366}
367
368#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
369
Simon Glassb1f7f582017-07-29 11:35:04 -0600370static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
371 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
372 s32 is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000373{
Simon Glass96f2af42017-07-29 11:35:07 -0600374 struct ahci_ioports *pp = &uc_priv->port[port];
Simon Glassd30e76c2017-07-29 11:35:05 -0600375 struct sata_port_regs *port_mmio = pp->port_mmio;
Stefano Babic771bfd12012-02-22 00:24:39 +0000376 u32 opts;
377 int sg_count = 0, cmd_slot = 0;
378
Simon Glass96f2af42017-07-29 11:35:07 -0600379 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
Stefano Babic771bfd12012-02-22 00:24:39 +0000380 if (32 == cmd_slot) {
381 printf("Can't find empty command slot!\n");
382 return 0;
383 }
384
385 /* Check xfer length */
386 if (buf_len > MAX_BYTES_PER_TRANS) {
387 printf("Max transfer length is %dB\n\r",
388 MAX_BYTES_PER_TRANS);
389 return 0;
390 }
391
392 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
393 if (buf && buf_len)
Simon Glassb1f7f582017-07-29 11:35:04 -0600394 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
Stefano Babic771bfd12012-02-22 00:24:39 +0000395 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
Eric Nelson998816b2013-06-15 16:09:55 -0700396 if (is_write) {
Stefano Babic771bfd12012-02-22 00:24:39 +0000397 opts |= 0x40;
Eric Nelson998816b2013-06-15 16:09:55 -0700398 flush_cache((ulong)buf, buf_len);
399 }
Stefano Babic771bfd12012-02-22 00:24:39 +0000400 ahci_fill_cmd_slot(pp, cmd_slot, opts);
401
Eric Nelson998816b2013-06-15 16:09:55 -0700402 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
Simon Glass96f2af42017-07-29 11:35:07 -0600403 writel_with_flush(1 << cmd_slot, &port_mmio->ci);
Stefano Babic771bfd12012-02-22 00:24:39 +0000404
Simon Glass96f2af42017-07-29 11:35:07 -0600405 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
406 0x1 << cmd_slot)) {
Stefano Babic771bfd12012-02-22 00:24:39 +0000407 printf("timeout exit!\n");
408 return -1;
409 }
Eric Nelson998816b2013-06-15 16:09:55 -0700410 invalidate_dcache_range((int)(pp->cmd_slot),
411 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
Stefano Babic771bfd12012-02-22 00:24:39 +0000412 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
413 pp->cmd_slot->status);
Eric Nelson998816b2013-06-15 16:09:55 -0700414 if (!is_write)
415 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
Stefano Babic771bfd12012-02-22 00:24:39 +0000416
417 return buf_len;
418}
419
Simon Glassc5fc2a32017-07-29 11:35:06 -0600420static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
Stefano Babic771bfd12012-02-22 00:24:39 +0000421{
Eric Nelson998816b2013-06-15 16:09:55 -0700422 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
423 struct sata_fis_h2d *cfis = &h2d;
Stefano Babic771bfd12012-02-22 00:24:39 +0000424
425 memset(cfis, 0, sizeof(struct sata_fis_h2d));
426 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
427 cfis->pm_port_c = 1 << 7;
428 cfis->command = ATA_CMD_SET_FEATURES;
429 cfis->features = SETFEATURES_XFER;
Simon Glassb1f7f582017-07-29 11:35:04 -0600430 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
Stefano Babic771bfd12012-02-22 00:24:39 +0000431
Simon Glassb1f7f582017-07-29 11:35:04 -0600432 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
Stefano Babic771bfd12012-02-22 00:24:39 +0000433}
434
Simon Glassb1f7f582017-07-29 11:35:04 -0600435static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
Stefano Babic771bfd12012-02-22 00:24:39 +0000436{
Simon Glass96f2af42017-07-29 11:35:07 -0600437 struct ahci_ioports *pp = &uc_priv->port[port];
Simon Glassd30e76c2017-07-29 11:35:05 -0600438 struct sata_port_regs *port_mmio = pp->port_mmio;
Stefano Babic771bfd12012-02-22 00:24:39 +0000439 u32 port_status;
440 u32 mem;
441 int timeout = 10000000;
442
443 debug("Enter start port: %d\n", port);
Simon Glass96f2af42017-07-29 11:35:07 -0600444 port_status = readl(&port_mmio->ssts);
Stefano Babic771bfd12012-02-22 00:24:39 +0000445 debug("Port %d status: %x\n", port, port_status);
446 if ((port_status & 0xf) != 0x03) {
447 printf("No Link on this port!\n");
448 return -1;
449 }
450
451 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
452 if (!mem) {
453 free(pp);
454 printf("No mem for table!\n");
455 return -ENOMEM;
456 }
457
458 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
459 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
460
461 /*
462 * First item in chunk of DMA memory: 32-slot command table,
463 * 32 bytes each in size
464 */
465 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
466 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
467 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
468
469 /*
470 * Second item: Received-FIS area, 256-Byte aligned
471 */
472 pp->rx_fis = mem;
473 mem += AHCI_RX_FIS_SZ;
474
475 /*
476 * Third item: data area for storing a single command
477 * and its scatter-gather table
478 */
479 pp->cmd_tbl = mem;
Tang Yuantian3f262d02015-07-09 14:37:30 +0800480 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
Stefano Babic771bfd12012-02-22 00:24:39 +0000481
482 mem += AHCI_CMD_TBL_HDR;
483
Simon Glass96f2af42017-07-29 11:35:07 -0600484 writel_with_flush(0x00004444, &port_mmio->dmacr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000485 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
Simon Glass96f2af42017-07-29 11:35:07 -0600486 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
487 writel_with_flush(pp->rx_fis, &port_mmio->fb);
Stefano Babic771bfd12012-02-22 00:24:39 +0000488
489 /* Enable FRE */
Simon Glass96f2af42017-07-29 11:35:07 -0600490 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
491 &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000492
493 /* Wait device ready */
Simon Glass96f2af42017-07-29 11:35:07 -0600494 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
Stefano Babic771bfd12012-02-22 00:24:39 +0000495 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
496 && --timeout)
497 ;
498 if (timeout <= 0) {
499 debug("Device not ready for BSY, DRQ and"
500 "ERR in TFD!\n");
501 return -1;
502 }
503
504 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
505 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
Simon Glass96f2af42017-07-29 11:35:07 -0600506 PORT_CMD_START, &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000507
508 debug("Exit start port %d\n", port);
509
510 return 0;
511}
512
Simon Glassc5fc2a32017-07-29 11:35:06 -0600513static void dwc_ahsata_print_info(struct blk_desc *pdev)
Stefano Babic771bfd12012-02-22 00:24:39 +0000514{
Stefano Babic771bfd12012-02-22 00:24:39 +0000515 printf("SATA Device Info:\n\r");
Stefano Babic771bfd12012-02-22 00:24:39 +0000516 printf("S/N: %s\n\rProduct model number: %s\n\r"
Soeren Moch71657f12019-03-01 13:10:58 +0100517 "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
Stefano Babic771bfd12012-02-22 00:24:39 +0000518 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
Stefano Babic771bfd12012-02-22 00:24:39 +0000519}
520
Simon Glassc5fc2a32017-07-29 11:35:06 -0600521static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
Stefano Babic771bfd12012-02-22 00:24:39 +0000522{
Eric Nelson998816b2013-06-15 16:09:55 -0700523 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
524 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600525 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000526
527 memset(cfis, 0, sizeof(struct sata_fis_h2d));
528
529 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
530 cfis->pm_port_c = 0x80; /* is command */
531 cfis->command = ATA_CMD_ID_ATA;
532
Simon Glassb1f7f582017-07-29 11:35:04 -0600533 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
534 READ_CMD);
Stefano Babic771bfd12012-02-22 00:24:39 +0000535 ata_swap_buf_le16(id, ATA_ID_WORDS);
536}
537
Simon Glassc5fc2a32017-07-29 11:35:06 -0600538static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
Stefano Babic771bfd12012-02-22 00:24:39 +0000539{
Simon Glassb1f7f582017-07-29 11:35:04 -0600540 uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
541 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
542 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
Stefano Babic771bfd12012-02-22 00:24:39 +0000543}
544
Simon Glassc5fc2a32017-07-29 11:35:06 -0600545static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
546 u32 blkcnt, u8 *buffer, int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000547{
Eric Nelson998816b2013-06-15 16:09:55 -0700548 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
549 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600550 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000551 u32 block;
552
553 block = start;
554
555 memset(cfis, 0, sizeof(struct sata_fis_h2d));
556
557 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
558 cfis->pm_port_c = 0x80; /* is command */
559 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
560 cfis->device = ATA_LBA;
561
562 cfis->device |= (block >> 24) & 0xf;
563 cfis->lba_high = (block >> 16) & 0xff;
564 cfis->lba_mid = (block >> 8) & 0xff;
565 cfis->lba_low = block & 0xff;
566 cfis->sector_count = (u8)(blkcnt & 0xff);
567
Simon Glassb1f7f582017-07-29 11:35:04 -0600568 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
569 ATA_SECT_SIZE * blkcnt, is_write) > 0)
Stefano Babic771bfd12012-02-22 00:24:39 +0000570 return blkcnt;
571 else
572 return 0;
573}
574
Simon Glassc5fc2a32017-07-29 11:35:06 -0600575static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000576{
Eric Nelson998816b2013-06-15 16:09:55 -0700577 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
578 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600579 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000580
581 memset(cfis, 0, sizeof(struct sata_fis_h2d));
582
583 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
584 cfis->pm_port_c = 0x80; /* is command */
585 cfis->command = ATA_CMD_FLUSH;
586
Simon Glassb1f7f582017-07-29 11:35:04 -0600587 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
Stefano Babic771bfd12012-02-22 00:24:39 +0000588}
589
Simon Glassc5fc2a32017-07-29 11:35:06 -0600590static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
591 lbaint_t blkcnt, u8 *buffer, int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000592{
Eric Nelson998816b2013-06-15 16:09:55 -0700593 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
594 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600595 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000596 u64 block;
597
598 block = (u64)start;
599
600 memset(cfis, 0, sizeof(struct sata_fis_h2d));
601
602 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
603 cfis->pm_port_c = 0x80; /* is command */
604
605 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
606 : ATA_CMD_READ_EXT;
607
608 cfis->lba_high_exp = (block >> 40) & 0xff;
609 cfis->lba_mid_exp = (block >> 32) & 0xff;
610 cfis->lba_low_exp = (block >> 24) & 0xff;
611 cfis->lba_high = (block >> 16) & 0xff;
612 cfis->lba_mid = (block >> 8) & 0xff;
613 cfis->lba_low = block & 0xff;
614 cfis->device = ATA_LBA;
615 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
616 cfis->sector_count = blkcnt & 0xff;
617
Simon Glassb1f7f582017-07-29 11:35:04 -0600618 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
619 ATA_SECT_SIZE * blkcnt, is_write) > 0)
Stefano Babic771bfd12012-02-22 00:24:39 +0000620 return blkcnt;
621 else
622 return 0;
623}
624
Simon Glassc5fc2a32017-07-29 11:35:06 -0600625static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000626{
Eric Nelson998816b2013-06-15 16:09:55 -0700627 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
628 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600629 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000630
631 memset(cfis, 0, sizeof(struct sata_fis_h2d));
632
633 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
634 cfis->pm_port_c = 0x80; /* is command */
635 cfis->command = ATA_CMD_FLUSH_EXT;
636
Simon Glassb1f7f582017-07-29 11:35:04 -0600637 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
Stefano Babic771bfd12012-02-22 00:24:39 +0000638}
639
Simon Glassc5fc2a32017-07-29 11:35:06 -0600640static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
Stefano Babic771bfd12012-02-22 00:24:39 +0000641{
Stefano Babic771bfd12012-02-22 00:24:39 +0000642 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
Simon Glassb1f7f582017-07-29 11:35:04 -0600643 uc_priv->flags |= SATA_FLAG_WCACHE;
Stefano Babic771bfd12012-02-22 00:24:39 +0000644 if (ata_id_has_flush(id))
Simon Glassb1f7f582017-07-29 11:35:04 -0600645 uc_priv->flags |= SATA_FLAG_FLUSH;
Stefano Babic771bfd12012-02-22 00:24:39 +0000646 if (ata_id_has_flush_ext(id))
Simon Glassb1f7f582017-07-29 11:35:04 -0600647 uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
Stefano Babic771bfd12012-02-22 00:24:39 +0000648}
649
Simon Glassc5fc2a32017-07-29 11:35:06 -0600650static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
651 lbaint_t blkcnt, const void *buffer,
652 int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000653{
654 u32 start, blks;
655 u8 *addr;
656 int max_blks;
657
658 start = blknr;
659 blks = blkcnt;
660 addr = (u8 *)buffer;
661
662 max_blks = ATA_MAX_SECTORS_LBA48;
663
664 do {
665 if (blks > max_blks) {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600666 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
667 max_blks, addr,
668 is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000669 return 0;
670 start += max_blks;
671 blks -= max_blks;
672 addr += ATA_SECT_SIZE * max_blks;
673 } else {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600674 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
675 addr, is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000676 return 0;
677 start += blks;
678 blks = 0;
679 addr += ATA_SECT_SIZE * blks;
680 }
681 } while (blks != 0);
682
683 return blkcnt;
684}
685
Simon Glassc5fc2a32017-07-29 11:35:06 -0600686static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
687 lbaint_t blkcnt, const void *buffer,
688 int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000689{
690 u32 start, blks;
691 u8 *addr;
692 int max_blks;
693
694 start = blknr;
695 blks = blkcnt;
696 addr = (u8 *)buffer;
697
698 max_blks = ATA_MAX_SECTORS;
699 do {
700 if (blks > max_blks) {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600701 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
702 max_blks, addr,
703 is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000704 return 0;
705 start += max_blks;
706 blks -= max_blks;
707 addr += ATA_SECT_SIZE * max_blks;
708 } else {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600709 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
710 addr, is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000711 return 0;
712 start += blks;
713 blks = 0;
714 addr += ATA_SECT_SIZE * blks;
715 }
716 } while (blks != 0);
717
718 return blkcnt;
719}
720
Simon Glassf89b2502017-07-29 11:35:12 -0600721static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
722{
723 u32 linkmap;
724 int i;
725
726 linkmap = uc_priv->link_port_map;
727
728 if (0 == linkmap) {
729 printf("No port device detected!\n");
730 return -ENXIO;
731 }
732
733 for (i = 0; i < uc_priv->n_ports; i++) {
734 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
735 if (ahci_port_start(uc_priv, (u8)i)) {
736 printf("Can not start port %d\n", i);
737 return 1;
738 }
739 uc_priv->hard_port_no = i;
740 break;
741 }
742 }
743
744 return 0;
745}
746
747static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
748 struct blk_desc *pdev)
749{
750 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
751 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
752 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
Simon Glassf89b2502017-07-29 11:35:12 -0600753 u8 port = uc_priv->hard_port_no;
754 ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
755
756 /* Identify device to get information */
757 dwc_ahsata_identify(uc_priv, id);
758
759 /* Serial number */
760 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
761 memcpy(pdev->product, serial, sizeof(serial));
762
763 /* Firmware version */
764 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
765 memcpy(pdev->revision, firmware, sizeof(firmware));
766
767 /* Product model */
768 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
769 memcpy(pdev->vendor, product, sizeof(product));
770
Soeren Moch71657f12019-03-01 13:10:58 +0100771 /* Total sectors */
772 pdev->lba = ata_id_n_sectors(id);
Simon Glassf89b2502017-07-29 11:35:12 -0600773
774 pdev->type = DEV_TYPE_HARDDISK;
775 pdev->blksz = ATA_SECT_SIZE;
776 pdev->lun = 0;
777
778 /* Check if support LBA48 */
779 if (ata_id_has_lba48(id)) {
780 pdev->lba48 = 1;
781 debug("Device support LBA48\n\r");
782 }
783
784 /* Get the NCQ queue depth from device */
785 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
786 uc_priv->flags |= ata_id_queue_depth(id);
787
788 /* Get the xfer mode from device */
789 dwc_ahsata_xfer_mode(uc_priv, id);
790
791 /* Get the write cache status from device */
792 dwc_ahsata_init_wcache(uc_priv, id);
793
794 /* Set the xfer mode to highest speed */
795 ahci_set_feature(uc_priv, port);
796
797 dwc_ahsata_print_info(pdev);
798
799 return 0;
800}
801
802/*
803 * SATA interface between low level driver and command layer
804 */
805static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
806 struct blk_desc *desc, ulong blknr,
807 lbaint_t blkcnt, void *buffer)
808{
809 u32 rc;
810
811 if (desc->lba48)
812 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
813 READ_CMD);
814 else
815 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
816 READ_CMD);
817
818 return rc;
819}
820
821static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
822 struct blk_desc *desc, ulong blknr,
823 lbaint_t blkcnt, const void *buffer)
824{
825 u32 rc;
826 u32 flags = uc_priv->flags;
827
828 if (desc->lba48) {
829 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
830 WRITE_CMD);
831 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
832 dwc_ahsata_flush_cache_ext(uc_priv);
833 } else {
834 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
835 WRITE_CMD);
836 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
837 dwc_ahsata_flush_cache(uc_priv);
838 }
839
840 return rc;
841}
842
Simon Glass0067b872017-07-29 11:35:16 -0600843#if !CONFIG_IS_ENABLED(AHCI)
Simon Glass22b08aa2017-07-29 11:35:11 -0600844static int ahci_init_one(int pdev)
845{
846 int rc;
847 struct ahci_uc_priv *uc_priv = NULL;
848
849 uc_priv = malloc(sizeof(struct ahci_uc_priv));
Ye Licc653ce2020-05-03 22:27:00 +0800850 if (!uc_priv)
851 return -ENOMEM;
852
Simon Glass22b08aa2017-07-29 11:35:11 -0600853 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
854 uc_priv->dev = pdev;
855
856 uc_priv->host_flags = ATA_FLAG_SATA
857 | ATA_FLAG_NO_LEGACY
858 | ATA_FLAG_MMIO
859 | ATA_FLAG_PIO_DMA
860 | ATA_FLAG_NO_ATAPI;
861
862 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
863
864 /* initialize adapter */
865 rc = ahci_host_init(uc_priv);
866 if (rc)
867 goto err_out;
868
869 ahci_print_info(uc_priv);
870
871 /* Save the uc_private struct to block device struct */
872 sata_dev_desc[pdev].priv = uc_priv;
873
874 return 0;
875
876err_out:
Ye Licc653ce2020-05-03 22:27:00 +0800877 if (uc_priv)
878 free(uc_priv);
Simon Glass22b08aa2017-07-29 11:35:11 -0600879 return rc;
880}
881
Simon Glassed82fcc2017-07-29 11:35:03 -0600882int init_sata(int dev)
883{
Simon Glassb1f7f582017-07-29 11:35:04 -0600884 struct ahci_uc_priv *uc_priv = NULL;
Simon Glassed82fcc2017-07-29 11:35:03 -0600885
886#if defined(CONFIG_MX6)
887 if (!is_mx6dq() && !is_mx6dqp())
888 return 1;
889#endif
890 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
891 printf("The sata index %d is out of ranges\n\r", dev);
892 return -1;
893 }
894
895 ahci_init_one(dev);
896
Simon Glassd30e76c2017-07-29 11:35:05 -0600897 uc_priv = sata_dev_desc[dev].priv;
Simon Glassed82fcc2017-07-29 11:35:03 -0600898
Simon Glassf89b2502017-07-29 11:35:12 -0600899 return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
Simon Glassed82fcc2017-07-29 11:35:03 -0600900}
901
902int reset_sata(int dev)
903{
Simon Glassb1f7f582017-07-29 11:35:04 -0600904 struct ahci_uc_priv *uc_priv;
Simon Glassed82fcc2017-07-29 11:35:03 -0600905 struct sata_host_regs *host_mmio;
906
907 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
908 printf("The sata index %d is out of ranges\n\r", dev);
909 return -1;
910 }
911
Simon Glassd30e76c2017-07-29 11:35:05 -0600912 uc_priv = sata_dev_desc[dev].priv;
Simon Glassb1f7f582017-07-29 11:35:04 -0600913 if (NULL == uc_priv)
Simon Glassed82fcc2017-07-29 11:35:03 -0600914 /* not initialized, so nothing to reset */
915 return 0;
916
Simon Glassd30e76c2017-07-29 11:35:05 -0600917 host_mmio = uc_priv->mmio_base;
Simon Glassed82fcc2017-07-29 11:35:03 -0600918 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
919 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
920 udelay(100);
921
922 return 0;
923}
924
Nikita Kiryanov66914042014-08-20 15:08:53 +0300925int sata_port_status(int dev, int port)
926{
927 struct sata_port_regs *port_mmio;
Simon Glassb1f7f582017-07-29 11:35:04 -0600928 struct ahci_uc_priv *uc_priv = NULL;
Nikita Kiryanov66914042014-08-20 15:08:53 +0300929
930 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
931 return -EINVAL;
932
933 if (sata_dev_desc[dev].priv == NULL)
934 return -ENODEV;
935
Simon Glassd30e76c2017-07-29 11:35:05 -0600936 uc_priv = sata_dev_desc[dev].priv;
937 port_mmio = uc_priv->port[port].port_mmio;
Nikita Kiryanov66914042014-08-20 15:08:53 +0300938
Simon Glass96f2af42017-07-29 11:35:07 -0600939 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
Nikita Kiryanov66914042014-08-20 15:08:53 +0300940}
941
Stefano Babic771bfd12012-02-22 00:24:39 +0000942/*
943 * SATA interface between low level driver and command layer
944 */
Tom Rini532e8672012-09-29 07:53:06 -0700945ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
Stefano Babic771bfd12012-02-22 00:24:39 +0000946{
Simon Glassc5fc2a32017-07-29 11:35:06 -0600947 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
Stefano Babic771bfd12012-02-22 00:24:39 +0000948
Simon Glassf89b2502017-07-29 11:35:12 -0600949 return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
950 buffer);
Stefano Babic771bfd12012-02-22 00:24:39 +0000951}
952
Tom Rini532e8672012-09-29 07:53:06 -0700953ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
Stefano Babic771bfd12012-02-22 00:24:39 +0000954{
Simon Glassd30e76c2017-07-29 11:35:05 -0600955 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
Stefano Babic771bfd12012-02-22 00:24:39 +0000956
Simon Glassf89b2502017-07-29 11:35:12 -0600957 return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
958 buffer);
Stefano Babic771bfd12012-02-22 00:24:39 +0000959}
960
961int scan_sata(int dev)
962{
Simon Glassd30e76c2017-07-29 11:35:05 -0600963 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
Simon Glass96f2af42017-07-29 11:35:07 -0600964 struct blk_desc *pdev = &sata_dev_desc[dev];
Stefano Babic771bfd12012-02-22 00:24:39 +0000965
Simon Glassf89b2502017-07-29 11:35:12 -0600966 return dwc_ahsata_scan_common(uc_priv, pdev);
Stefano Babic771bfd12012-02-22 00:24:39 +0000967}
Simon Glass0067b872017-07-29 11:35:16 -0600968#endif /* CONFIG_IS_ENABLED(AHCI) */
969
970#if CONFIG_IS_ENABLED(AHCI)
971
972int dwc_ahsata_port_status(struct udevice *dev, int port)
973{
974 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
975 struct sata_port_regs *port_mmio;
976
977 port_mmio = uc_priv->port[port].port_mmio;
978 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
979}
980
981int dwc_ahsata_bus_reset(struct udevice *dev)
982{
983 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
984 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
985
986 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
987 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
988 udelay(100);
989
990 return 0;
991}
992
993int dwc_ahsata_scan(struct udevice *dev)
994{
995 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
996 struct blk_desc *desc;
997 struct udevice *blk;
998 int ret;
999
1000 /*
1001 * Create only one block device and do detection
1002 * to make sure that there won't be a lot of
1003 * block devices created
1004 */
1005 device_find_first_child(dev, &blk);
1006 if (!blk) {
1007 ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
1008 IF_TYPE_SATA, -1, 512, 0, &blk);
1009 if (ret) {
1010 debug("Can't create device\n");
1011 return ret;
1012 }
1013 }
1014
1015 desc = dev_get_uclass_platdata(blk);
1016 ret = dwc_ahsata_scan_common(uc_priv, desc);
1017 if (ret) {
1018 debug("%s: Failed to scan bus\n", __func__);
1019 return ret;
1020 }
1021
1022 return 0;
1023}
1024
1025int dwc_ahsata_probe(struct udevice *dev)
1026{
1027 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1028 int ret;
1029
Soeren Moch5569bbd2019-03-01 13:10:59 +01001030#if defined(CONFIG_MX6)
1031 setup_sata();
1032#endif
Simon Glass0067b872017-07-29 11:35:16 -06001033 uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
1034 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
1035 uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
1036
1037 /* initialize adapter */
1038 ret = ahci_host_init(uc_priv);
1039 if (ret)
1040 return ret;
1041
1042 ahci_print_info(uc_priv);
1043
1044 return dwc_ahci_start_ports(uc_priv);
1045}
1046
1047static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
1048 lbaint_t blkcnt, void *buffer)
1049{
1050 struct blk_desc *desc = dev_get_uclass_platdata(blk);
1051 struct udevice *dev = dev_get_parent(blk);
1052 struct ahci_uc_priv *uc_priv;
1053
1054 uc_priv = dev_get_uclass_priv(dev);
1055 return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
1056}
1057
1058static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
1059 lbaint_t blkcnt, const void *buffer)
1060{
1061 struct blk_desc *desc = dev_get_uclass_platdata(blk);
1062 struct udevice *dev = dev_get_parent(blk);
1063 struct ahci_uc_priv *uc_priv;
1064
1065 uc_priv = dev_get_uclass_priv(dev);
1066 return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
1067}
1068
1069static const struct blk_ops dwc_ahsata_blk_ops = {
1070 .read = dwc_ahsata_read,
1071 .write = dwc_ahsata_write,
1072};
1073
1074U_BOOT_DRIVER(dwc_ahsata_blk) = {
1075 .name = "dwc_ahsata_blk",
1076 .id = UCLASS_BLK,
1077 .ops = &dwc_ahsata_blk_ops,
1078};
1079
Soeren Moch5569bbd2019-03-01 13:10:59 +01001080#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
1081struct ahci_ops dwc_ahsata_ahci_ops = {
1082 .port_status = dwc_ahsata_port_status,
1083 .reset = dwc_ahsata_bus_reset,
1084 .scan = dwc_ahsata_scan,
1085};
1086
1087static const struct udevice_id dwc_ahsata_ahci_ids[] = {
1088 { .compatible = "fsl,imx6q-ahci" },
1089 { }
1090};
1091
1092U_BOOT_DRIVER(dwc_ahsata_ahci) = {
1093 .name = "dwc_ahsata_ahci",
1094 .id = UCLASS_AHCI,
1095 .of_match = dwc_ahsata_ahci_ids,
1096 .ops = &dwc_ahsata_ahci_ops,
1097 .probe = dwc_ahsata_probe,
1098};
1099#endif
Simon Glass0067b872017-07-29 11:35:16 -06001100#endif