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git01.mediatek.com / filogic / uboot / cc51012bd5e83b23b1e8d0258fe1251f1e6dfdcb / . / cpu / ixp / npe / include / IxOsalOsIxp400.h
blob: 44a94fb30fe93fa7dd6f994378e71fdd72bbd93c [file] [log] [blame]
Wolfgang Denk4646d2a2006-05-30 15:56:48 +0200[diff] [blame]1/**
2 * @file IxOsalOsIxp400.h
3 *
4 * @brief OS and platform specific definitions
5 *
6 * Design Notes:
7 *
8 * @par
9 * IXP400 SW Release version 2.0
10 *
11 * -- Copyright Notice --
12 *
13 * @par
14 * Copyright 2001-2005, Intel Corporation.
15 * All rights reserved.
16 *
17 * @par
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. Neither the name of the Intel Corporation nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * @par
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 *
43 * @par
44 * -- End of Copyright Notice --
45 */
46
47#ifndef IxOsalOsIxp400_H
48#define IxOsalOsIxp400_H
49
50#define BIT(x) (1<<(x))
51
52#define IXP425_EthA_BASE 0xc8009000
53#define IXP425_EthB_BASE 0xc800a000
54
55#define IXP425_PSMA_BASE 0xc8006000
56#define IXP425_PSMB_BASE 0xc8007000
57#define IXP425_PSMC_BASE 0xc8008000
58
59#define IXP425_PERIPHERAL_BASE 0xc8000000
60
61#define IXP425_QMGR_BASE 0x60000000
62#define IXP425_OSTS 0xC8005000
63
64#define IXP425_INT_LVL_NPEA 0
65#define IXP425_INT_LVL_NPEB 1
66#define IXP425_INT_LVL_NPEC 2
67
68#define IXP425_INT_LVL_QM1 3
69#define IXP425_INT_LVL_QM2 4
70
71#define IXP425_EXPANSION_BUS_BASE1 0x50000000
72#define IXP425_EXPANSION_BUS_BASE2 0x50000000
73#define IXP425_EXPANSION_BUS_CS1_BASE 0x51000000
74
75#define IXP425_EXP_CONFIG_BASE 0xC4000000
76
77/* physical addresses to be used when requesting memory with IX_OSAL_MEM_MAP */
78#define IX_OSAL_IXP400_INTC_PHYS_BASE IXP425_INTC_BASE
79#define IX_OSAL_IXP400_GPIO_PHYS_BASE IXP425_GPIO_BASE
80#define IX_OSAL_IXP400_UART1_PHYS_BASE IXP425_UART1_BASE
81#define IX_OSAL_IXP400_UART2_PHYS_BASE IXP425_UART2_BASE
82#define IX_OSAL_IXP400_ETHA_PHYS_BASE IXP425_EthA_BASE
83#define IX_OSAL_IXP400_ETHB_PHYS_BASE IXP425_EthB_BASE
84#define IX_OSAL_IXP400_NPEA_PHYS_BASE IXP425_NPEA_BASE
85#define IX_OSAL_IXP400_NPEB_PHYS_BASE IXP425_NPEB_BASE
86#define IX_OSAL_IXP400_NPEC_PHYS_BASE IXP425_NPEC_BASE
87#define IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE IXP425_PERIPHERAL_BASE
88#define IX_OSAL_IXP400_QMGR_PHYS_BASE IXP425_QMGR_BASE
89#define IX_OSAL_IXP400_OSTS_PHYS_BASE IXP425_TIMER_BASE
90#define IX_OSAL_IXP400_USB_PHYS_BASE IXP425_USB_BASE
91#define IX_OSAL_IXP400_EXP_CFG_PHYS_BASE IXP425_EXP_CFG_BASE
92#define IX_OSAL_IXP400_EXP_BUS_PHYS_BASE IXP425_EXP_BUS_BASE2
93#define IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE IXP425_EXP_BUS_BASE1
94#define IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE IXP425_EXP_BUS_CS0_BASE
95#define IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE IXP425_EXP_BUS_CS1_BASE
96#define IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE IXP425_EXP_BUS_CS4_BASE
97#define IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE IXP425_EXP_CFG_BASE
98#define IX_OSAL_IXP400_PCI_CFG_PHYS_BASE IXP425_PCI_CFG_BASE
99
100/* map sizes to be used when requesting memory with IX_OSAL_MEM_MAP */
101#define IX_OSAL_IXP400_QMGR_MAP_SIZE (0x4000) /**< Queue Manager map size */
102#define IX_OSAL_IXP400_PERIPHERAL_MAP_SIZE (0xC000) /**< Peripheral space map size */
103#define IX_OSAL_IXP400_UART1_MAP_SIZE (0x1000) /**< UART1 map size */
104#define IX_OSAL_IXP400_UART2_MAP_SIZE (0x1000) /**< UART2 map size */
105#define IX_OSAL_IXP400_PMU_MAP_SIZE (0x1000) /**< PMU map size */
106#define IX_OSAL_IXP400_OSTS_MAP_SIZE (0x1000) /**< OS Timers map size */
107#define IX_OSAL_IXP400_NPEA_MAP_SIZE (0x1000) /**< NPE A map size */
108#define IX_OSAL_IXP400_NPEB_MAP_SIZE (0x1000) /**< NPE B map size */
109#define IX_OSAL_IXP400_NPEC_MAP_SIZE (0x1000) /**< NPE C map size */
110#define IX_OSAL_IXP400_ETHA_MAP_SIZE (0x1000) /**< Eth A map size */
111#define IX_OSAL_IXP400_ETHB_MAP_SIZE (0x1000) /**< Eth B map size */
112#define IX_OSAL_IXP400_USB_MAP_SIZE (0x1000) /**< USB map size */
113#define IX_OSAL_IXP400_GPIO_MAP_SIZE (0x1000) /**< GPIO map size */
114#define IX_OSAL_IXP400_EXP_REG_MAP_SIZE (0x1000) /**< Exp Bus Config Registers map size */
115#define IX_OSAL_IXP400_EXP_BUS_MAP_SIZE (0x08000000) /**< Expansion bus map size */
116#define IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE (0x01000000) /**< CS0 map size */
117#define IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE (0x01000000) /**< CS1 map size */
118#define IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE (0x01000000) /**< CS4 map size */
119#define IX_OSAL_IXP400_PCI_CFG_MAP_SIZE (0x1000) /**< PCI Bus Config Registers map size */
120
121#define IX_OSAL_IXP400_EXP_FUSE (IXP425_EXP_CONFIG_BASE + 0x28)
122#define IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE 0xC800C000
123#define IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE 0x1000
124
125/*
126 * Interrupt Levels
127 */
128#define IX_OSAL_IXP400_NPEA_IRQ_LVL (0)
129#define IX_OSAL_IXP400_NPEB_IRQ_LVL (1)
130#define IX_OSAL_IXP400_NPEC_IRQ_LVL (2)
131#define IX_OSAL_IXP400_QM1_IRQ_LVL (3)
132#define IX_OSAL_IXP400_QM2_IRQ_LVL (4)
133#define IX_OSAL_IXP400_TIMER1_IRQ_LVL (5)
134#define IX_OSAL_IXP400_GPIO0_IRQ_LVL (6)
135#define IX_OSAL_IXP400_GPIO1_IRQ_LVL (7)
136#define IX_OSAL_IXP400_PCI_INT_IRQ_LVL (8)
137#define IX_OSAL_IXP400_PCI_DMA1_IRQ_LVL (9)
138#define IX_OSAL_IXP400_PCI_DMA2_IRQ_LVL (10)
139#define IX_OSAL_IXP400_TIMER2_IRQ_LVL (11)
140#define IX_OSAL_IXP400_USB_IRQ_LVL (12)
141#define IX_OSAL_IXP400_UART2_IRQ_LVL (13)
142#define IX_OSAL_IXP400_TIMESTAMP_IRQ_LVL (14)
143#define IX_OSAL_IXP400_UART1_IRQ_LVL (15)
144#define IX_OSAL_IXP400_WDOG_IRQ_LVL (16)
145#define IX_OSAL_IXP400_AHB_PMU_IRQ_LVL (17)
146#define IX_OSAL_IXP400_XSCALE_PMU_IRQ_LVL (18)
147#define IX_OSAL_IXP400_GPIO2_IRQ_LVL (19)
148#define IX_OSAL_IXP400_GPIO3_IRQ_LVL (20)
149#define IX_OSAL_IXP400_GPIO4_IRQ_LVL (21)
150#define IX_OSAL_IXP400_GPIO5_IRQ_LVL (22)
151#define IX_OSAL_IXP400_GPIO6_IRQ_LVL (23)
152#define IX_OSAL_IXP400_GPIO7_IRQ_LVL (24)
153#define IX_OSAL_IXP400_GPIO8_IRQ_LVL (25)
154#define IX_OSAL_IXP400_GPIO9_IRQ_LVL (26)
155#define IX_OSAL_IXP400_GPIO10_IRQ_LVL (27)
156#define IX_OSAL_IXP400_GPIO11_IRQ_LVL (28)
157#define IX_OSAL_IXP400_GPIO12_IRQ_LVL (29)
158#define IX_OSAL_IXP400_SW_INT1_IRQ_LVL (30)
159#define IX_OSAL_IXP400_SW_INT2_IRQ_LVL (31)
160
161/* USB interrupt level mask */
162#define IX_OSAL_IXP400_INT_LVL_USB IRQ_IXP425_USB
163
164/* USB IRQ */
165#define IX_OSAL_IXP400_USB_IRQ IRQ_IXP425_USB
166
167/*
168 * OS name retrieval
169 */
170#define IX_OSAL_OEM_OS_NAME_GET(name, limit) \
171ixOsalOsIxp400NameGet((INT8*)(name), (INT32) (limit))
172
173/*
174 * OS version retrieval
175 */
176#define IX_OSAL_OEM_OS_VERSION_GET(version, limit) \
177ixOsalOsIxp400VersionGet((INT8*)(version), (INT32) (limit))
178
179/*
180 * Function to retrieve the OS name
181 */
182PUBLIC IX_STATUS ixOsalOsIxp400NameGet(INT8* osName, INT32 maxSize);
183
184/*
185 * Function to retrieve the OS version
186 */
187PUBLIC IX_STATUS ixOsalOsIxp400VersionGet(INT8* osVersion, INT32 maxSize);
188
189/*
190 * TimestampGet
191 */
192PUBLIC UINT32 ixOsalOsIxp400TimestampGet (void);
193
194/*
195 * Timestamp
196 */
197#define IX_OSAL_OEM_TIMESTAMP_GET ixOsalOsIxp400TimestampGet
198
199
200/*
201 * Timestamp resolution
202 */
203PUBLIC UINT32 ixOsalOsIxp400TimestampResolutionGet (void);
204
205#define IX_OSAL_OEM_TIMESTAMP_RESOLUTION_GET ixOsalOsIxp400TimestampResolutionGet
206
207/*
208 * Retrieves the system clock rate
209 */
210PUBLIC UINT32 ixOsalOsIxp400SysClockRateGet (void);
211
212#define IX_OSAL_OEM_SYS_CLOCK_RATE_GET ixOsalOsIxp400SysClockRateGet
213
214/*
215 * required by FS but is not really platform-specific.
216 */
217#define IX_OSAL_OEM_TIME_GET(pTv) ixOsalTimeGet(pTv)
218
219
220
221/* linux map/unmap functions */
222PUBLIC void ixOsalLinuxMemMap (IxOsalMemoryMap * map);
223
224PUBLIC void ixOsalLinuxMemUnmap (IxOsalMemoryMap * map);
225
226
227/*********************
228 * Memory map
229 ********************/
230
231/* Global memmap only visible to IO MEM module */
232
233#ifdef IxOsalIoMem_C
234
235IxOsalMemoryMap ixOsalGlobalMemoryMap[] = {
236 {
237 /* Global BE and LE_AC map */
238 IX_OSAL_STATIC_MAP, /* type */
239 0x00000000, /* physicalAddress */
240 0x30000000, /* size */
241 0x00000000, /* virtualAddress */
242 NULL, /* mapFunction */
243 NULL, /* unmapFunction */
244 0, /* refCount */
245 IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
246 "global_low" /* name */
247 },
248
249 /* SDRAM LE_DC alias */
250 {
251 IX_OSAL_STATIC_MAP, /* type */
252 0x00000000, /* physicalAddress */
253 0x10000000, /* size */
254 0x30000000, /* virtualAddress */
255 NULL, /* mapFunction */
256 NULL, /* unmapFunction */
257 0, /* refCount */
258 IX_OSAL_LE_DC, /* endianType */
259 "sdram_dc" /* name */
260 },
261
262 /* QMGR LE_DC alias */
263 {
264 IX_OSAL_STATIC_MAP, /* type */
265 0x60000000, /* physicalAddress */
266 0x00100000, /* size */
267 0x60000000, /* virtualAddress */
268 NULL, /* mapFunction */
269 NULL, /* unmapFunction */
270 0, /* refCount */
271 IX_OSAL_LE_DC, /* endianType */
272 "qmgr_dc" /* name */
273 },
274
275 /* QMGR BE alias */
276 {
277 IX_OSAL_STATIC_MAP, /* type */
278 0x60000000, /* physicalAddress */
279 0x00100000, /* size */
280 0x60000000, /* virtualAddress */
281 NULL, /* mapFunction */
282 NULL, /* unmapFunction */
283 0, /* refCount */
284 IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
285 "qmgr_be" /* name */
286 },
287
288 /* Global BE and LE_AC map */
289 {
290 IX_OSAL_STATIC_MAP, /* type */
291 0x40000000, /* physicalAddress */
292 0x20000000, /* size */
293 0x40000000, /* virtualAddress */
294 NULL, /* mapFunction */
295 NULL, /* unmapFunction */
296 0, /* refCount */
297 IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
298 "Misc Cfg" /* name */
299 },
300
301 /* Global BE and LE_AC map */
302 {
303 IX_OSAL_STATIC_MAP, /* type */
304 0x70000000, /* physicalAddress */
305 0x8FFFFFFF, /* size */
306 0x70000000, /* virtualAddress */
307 NULL, /* mapFunction */
308 NULL, /* unmapFunction */
309 0, /* refCount */
310 IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
311 "Exp Cfg" /* name */
312 },
313};
314
315#endif /* IxOsalIoMem_C */
316#endif /* #define IxOsalOsIxp400_H */