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git01.mediatek.com / filogic / uboot / cc46bc7faba0f33c154cddd1686e3b35086968e0 / . / include / configs / bf548-ezkit.h
blob: 1c035cfcadad70948244e0ba5851a0048de5d51e [file] [log] [blame]
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]1/*
2 * U-boot - Configuration file for BF548 STAMP board
3 */
4
5#ifndef __CONFIG_BF548_EZKIT_H__
6#define __CONFIG_BF548_EZKIT_H__
7
Mike Frysinger18a407c2009-04-24 17:22:40 -0400[diff] [blame]8#include <asm/config-pre.h>
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]9
10
11/*
12 * Processor Settings
13 */
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]14#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
15
16
17/*
18 * Clock Settings
19 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
20 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
21 */
22/* CONFIG_CLKIN_HZ is any value in Hz */
23#define CONFIG_CLKIN_HZ 25000000
24/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
25/* 1 = CLKIN / 2 */
26#define CONFIG_CLKIN_HALF 0
27/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
28/* 1 = bypass PLL */
29#define CONFIG_PLL_BYPASS 0
30/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
31/* Values can range from 0-63 (where 0 means 64) */
32#define CONFIG_VCO_MULT 21
33/* CCLK_DIV controls the core clock divider */
34/* Values can be 1, 2, 4, or 8 ONLY */
35#define CONFIG_CCLK_DIV 1
36/* SCLK_DIV controls the system clock divider */
37/* Values can range from 1-15 */
38#define CONFIG_SCLK_DIV 4
39
40
41/*
42 * Memory Settings
43 */
44#define CONFIG_MEM_ADD_WDTH 10
45#define CONFIG_MEM_SIZE 64
46
47#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
48#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
49#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
50
51/* Default EZ-Kit bank mapping:
52 * Async Bank 0 - 32MB Burst Flash
53 * Async Bank 1 - Ethernet
54 * Async Bank 2 - Nothing
55 * Async Bank 3 - Nothing
56 */
57#define CONFIG_EBIU_AMGCTL_VAL 0xFF
58#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
59#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
60#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
61#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
62
Mike Frysingera2306572009-06-14 21:23:27 -0400[diff] [blame]63#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]64#define CONFIG_SYS_MALLOC_LEN (768 * 1024)
65
66
67/*
68 * Network Settings
69 */
70#define ADI_CMDS_NETWORK 1
Ben Warrenfbfdd3a2009-07-20 22:01:11 -0700[diff] [blame]71#define CONFIG_NET_MULTI
72#define CONFIG_SMC911X 1
73#define CONFIG_SMC911X_BASE 0x24000000
74#define CONFIG_SMC911X_16_BIT
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]75#define CONFIG_HOSTNAME bf548-ezkit
76/* Uncomment next line to use fixed MAC address */
77/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
78
79
80/*
81 * Flash Settings
82 */
83#define CONFIG_FLASH_CFI_DRIVER
84#define CONFIG_SYS_FLASH_BASE 0x20000000
85#define CONFIG_SYS_FLASH_CFI
86#define CONFIG_SYS_FLASH_PROTECTION
87#define CONFIG_SYS_MAX_FLASH_BANKS 1
88#define CONFIG_SYS_MAX_FLASH_SECT 259
89
90
91/*
92 * SPI Settings
93 */
94#define CONFIG_BFIN_SPI
95#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysinger9a4406462009-06-14 22:29:35 -0400[diff] [blame]96#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]97#define CONFIG_SPI_FLASH
98#define CONFIG_SPI_FLASH_STMICRO
99
100
101/*
102 * Env Storage Settings
103 */
104#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
105#define CONFIG_ENV_IS_IN_SPI_FLASH
106#define CONFIG_ENV_OFFSET 0x10000
107#define CONFIG_ENV_SIZE 0x2000
108#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysinger45b57bd2009-07-21 22:17:36 -0400[diff] [blame]109#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]110#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
111#define CONFIG_ENV_IS_IN_NAND
112#define CONFIG_ENV_OFFSET 0x40000
113#define CONFIG_ENV_SIZE 0x20000
114#else
115#define CONFIG_ENV_IS_IN_FLASH 1
116#define CONFIG_ENV_ADDR 0x20002000
117#define CONFIG_ENV_OFFSET 0x2000
118#define CONFIG_ENV_SIZE 0x2000
119#define CONFIG_ENV_SECT_SIZE (128 * 1024)
Mike Frysinger45b57bd2009-07-21 22:17:36 -0400[diff] [blame]120#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]121#endif
122
123
124/*
125 * NAND Settings
126 */
127#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
128#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
129# define CONFIG_BFIN_NFC_BOOTROM_ECC
130#endif
131#define CONFIG_DRIVER_NAND_BFIN
132#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
133#define CONFIG_SYS_MAX_NAND_DEVICE 1
134#define NAND_MAX_CHIPS 1
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]135
136
137/*
138 * I2C Settings
139 */
140#define CONFIG_BFIN_TWI_I2C 1
141#define CONFIG_HARD_I2C 1
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]142
143
144/*
145 * SATA
146 */
147#if !defined(__ADSPBF544__)
148#define CONFIG_LIBATA
149#define CONFIG_SYS_SATA_MAX_DEVICE 1
150#define CONFIG_LBA48
151#define CONFIG_PATA_BFIN
152#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800
153#define CONFIG_BFIN_ATA_MODE XFER_PIO_4
154#endif
155
156
157/*
158 * SDH Settings
159 */
160#if !defined(__ADSPBF544__)
Cliff Caie4638922009-11-20 08:24:43 +0000[diff] [blame]161#define CONFIG_GENERIC_MMC
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]162#define CONFIG_MMC
163#define CONFIG_BFIN_SDH
164#endif
165
166
167/*
168 * USB Settings
169 */
170#if !defined(__ADSPBF544__)
171#define CONFIG_USB
172#define CONFIG_MUSB_HCD
173#define CONFIG_USB_BLACKFIN
174#define CONFIG_USB_STORAGE
175#define CONFIG_MUSB_TIMEOUT 100000
176#endif
177
178
179/*
180 * Misc Settings
181 */
182#define CONFIG_BOARD_EARLY_INIT_F
Mike Frysingercc64ba62010-10-19 18:02:43 -0400[diff] [blame]183#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]184#define CONFIG_RTC_BFIN
185#define CONFIG_UART_CONSOLE 1
Mike Frysinger55c5d712010-09-29 20:24:16 +0000[diff] [blame]186#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]187
188#ifndef __ADSPBF542__
189/* Don't waste time transferring a logo over the UART */
190# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
191# define CONFIG_VIDEO
192# endif
193# define CONFIG_DEB_DMA_URGENT
194#endif
195
196/* Define if want to do post memory test */
197#undef CONFIG_POST
198#ifdef CONFIG_POST
199#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
200#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
201#endif
202
203
204/*
205 * Pull in common ADI header for remaining command/environment setup
206 */
207#include <configs/bfin_adi_common.h>
208
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]209#endif