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wdenk9f664dd2004-06-09 21:50:45 +00001/*
wdenk9e930b62004-06-19 21:19:10 +00002 * cpu/mc9328/serial.c
3 *
wdenk9f664dd2004-06-09 21:50:45 +00004 * (c) Copyright 2004
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
7 *
8 * Ming-Len Wu <minglen_wu@techware.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
wdenk9f664dd2004-06-09 21:50:45 +000026#include <common.h>
27#include <mc9328.h>
28
wdenk9e930b62004-06-19 21:19:10 +000029#if defined(CONFIG_UART1)
wdenk9f664dd2004-06-09 21:50:45 +000030/* GPIO PORT B */
31
32#define reg_GIUS MX1_GIUS_C
33#define reg_GPR MX1_GPR_B
34#define GPIO_MASK 0xFFFFE1FF
35#define UART_BASE 0x00206000
36
wdenk9f664dd2004-06-09 21:50:45 +000037#elif defined (CONFIG_UART2)
38/* GPIO PORT C */
39
40#define reg_GIUS MX1_GIUS_C
41#define reg_GPR MX1_GPR_C
42#define GPIO_MASK 0x0FFFFFFF
43#define UART_BASE 0x207000
44
wdenk9e930b62004-06-19 21:19:10 +000045#endif
wdenk9f664dd2004-06-09 21:50:45 +000046
47#define reg_URXD (*((volatile u32 *)(UART_BASE+0x00)))
48#define reg_UTXD (*((volatile u32 *)(UART_BASE+0x40)))
49#define reg_UCR1 (*((volatile u32 *)(UART_BASE+0x80)))
50#define reg_UCR2 (*((volatile u32 *)(UART_BASE+0x84)))
51#define reg_UCR3 (*((volatile u32 *)(UART_BASE+0x88)))
52#define reg_UCR4 (*((volatile u32 *)(UART_BASE+0x8C)))
53#define reg_UFCR (*((volatile u32 *)(UART_BASE+0x90)))
54#define reg_USR1 (*((volatile u32 *)(UART_BASE+0x94)))
55#define reg_USR2 (*((volatile u32 *)(UART_BASE+0x98)))
56#define reg_UESC (*((volatile u32 *)(UART_BASE+0x9C)))
57#define reg_UTIM (*((volatile u32 *)(UART_BASE+0xA0)))
58#define reg_UBIR (*((volatile u32 *)(UART_BASE+0xA4)))
59#define reg_UBMR (*((volatile u32 *)(UART_BASE+0xA8)))
60#define reg_UBRC (*((volatile u32 *)(UART_BASE+0xAC)))
61
62#define TXFE_MASK 0x4000 /* Tx buffer empty */
63#define RDR_MASK 0x0001 /* receive data ready */
64
wdenk9f664dd2004-06-09 21:50:45 +000065void serial_setbrg (void) {
66
wdenk9e930b62004-06-19 21:19:10 +000067 /* config I/O pins for UART */
wdenk9f664dd2004-06-09 21:50:45 +000068 reg_GIUS &= GPIO_MASK;
69 reg_GPR &= GPIO_MASK;
70
wdenk9e930b62004-06-19 21:19:10 +000071 /* config UART */
wdenk9f664dd2004-06-09 21:50:45 +000072 reg_UCR1 = 5;
73 reg_UCR2 = 0x4027;
74 reg_UCR4 = 1;
75 reg_UFCR = 0xA81;
76
77 reg_UBIR = 0xF;
78 reg_UBMR = 0x8A;
79 reg_UBRC = 8;
80}
81
wdenk9f664dd2004-06-09 21:50:45 +000082/*
83 * Initialise the serial port with the given baudrate. The settings
84 * are always 8 data bits, no parity, 1 stop bit, no start bits.
85 *
86 */
wdenk9e930b62004-06-19 21:19:10 +000087
wdenk9f664dd2004-06-09 21:50:45 +000088int serial_init (void) {
89 serial_setbrg ();
90
91 return (0);
92}
93
wdenk9f664dd2004-06-09 21:50:45 +000094/*
95 * Read a single byte from the serial port. Returns 1 on success, 0
96 * otherwise. When the function is succesfull, the character read is
97 * written into its argument c.
98 */
99int serial_getc (void) {
100
101 while (!(reg_USR2 & RDR_MASK)) ; /* wait until RDR bit set */
102
103 return (u8)reg_URXD;
104}
105
wdenk9f664dd2004-06-09 21:50:45 +0000106/*
107 * Output a single byte to the serial port.
108 */
109void serial_putc (const char c) {
110
111 while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */
112
113 reg_UTXD = (u16) c;
114
115 if (c == '\n') { /* carriage return ? append line-feed */
116 while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */
117 reg_UTXD = '\r';
118 }
119
120}
121
wdenk9f664dd2004-06-09 21:50:45 +0000122/*
123 * Test whether a character is in the RX buffer
124 */
125int serial_tstc (void) {
126 return reg_USR2 & RDR_MASK;
127}
128
wdenk9f664dd2004-06-09 21:50:45 +0000129void serial_puts (const char *s) {
130 while (*s) {
131 serial_putc (*s++);
132 }
133}