Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 |
| 4 | * David Feng <fenghua@phytium.com.cn> |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 1ea9789 | 2020-05-10 11:40:00 -0600 | [diff] [blame] | 8 | #include <bootstage.h> |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 9 | #include <command.h> |
Simon Glass | 45c7890 | 2019-11-14 12:57:26 -0700 | [diff] [blame] | 10 | #include <time.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 11 | #include <asm/global_data.h> |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 12 | #include <asm/system.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 13 | #include <linux/bitops.h> |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 14 | |
Andre Przywara | de223fd | 2016-11-03 00:56:25 +0000 | [diff] [blame] | 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 17 | /* |
| 18 | * Generic timer implementation of get_tbclk() |
| 19 | */ |
| 20 | unsigned long get_tbclk(void) |
| 21 | { |
| 22 | unsigned long cntfrq; |
| 23 | asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq)); |
| 24 | return cntfrq; |
| 25 | } |
| 26 | |
Andre Przywara | 60b7865 | 2018-06-27 01:42:52 +0100 | [diff] [blame] | 27 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008585 |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 28 | /* |
Andre Przywara | 60b7865 | 2018-06-27 01:42:52 +0100 | [diff] [blame] | 29 | * FSL erratum A-008585 says that the ARM generic timer counter "has the |
| 30 | * potential to contain an erroneous value for a small number of core |
| 31 | * clock cycles every time the timer value changes". |
| 32 | * This sometimes leads to a consecutive counter read returning a lower |
| 33 | * value than the previous one, thus reporting the time to go backwards. |
| 34 | * The workaround is to read the counter twice and only return when the value |
| 35 | * was the same in both reads. |
| 36 | * Assumes that the CPU runs in much higher frequency than the timer. |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 37 | */ |
| 38 | unsigned long timer_read_counter(void) |
| 39 | { |
| 40 | unsigned long cntpct; |
York Sun | a7686cf | 2015-03-20 19:28:05 -0700 | [diff] [blame] | 41 | unsigned long temp; |
Andre Przywara | 60b7865 | 2018-06-27 01:42:52 +0100 | [diff] [blame] | 42 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 43 | isb(); |
| 44 | asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); |
York Sun | a7686cf | 2015-03-20 19:28:05 -0700 | [diff] [blame] | 45 | asm volatile("mrs %0, cntpct_el0" : "=r" (temp)); |
| 46 | while (temp != cntpct) { |
| 47 | asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); |
| 48 | asm volatile("mrs %0, cntpct_el0" : "=r" (temp)); |
| 49 | } |
Andre Przywara | 60b7865 | 2018-06-27 01:42:52 +0100 | [diff] [blame] | 50 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 51 | return cntpct; |
| 52 | } |
Andre Przywara | d1de0bb | 2018-06-27 01:42:53 +0100 | [diff] [blame] | 53 | #elif CONFIG_SUNXI_A64_TIMER_ERRATUM |
| 54 | /* |
| 55 | * This erratum sometimes flips the lower 11 bits of the counter value |
| 56 | * to all 0's or all 1's, leading to jumps forwards or backwards. |
| 57 | * Backwards jumps might be interpreted all roll-overs and be treated as |
| 58 | * huge jumps forward. |
| 59 | * The workaround is to check whether the lower 11 bits of the counter are |
| 60 | * all 0 or all 1, then discard this value and read again. |
| 61 | * This occasionally discards valid values, but will catch all erroneous |
| 62 | * reads and fixes the problem reliably. Also this mostly requires only a |
| 63 | * single read, so does not have any significant overhead. |
| 64 | * The algorithm was conceived by Samuel Holland. |
| 65 | */ |
| 66 | unsigned long timer_read_counter(void) |
| 67 | { |
| 68 | unsigned long cntpct; |
| 69 | |
| 70 | isb(); |
| 71 | do { |
| 72 | asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); |
| 73 | } while (((cntpct + 1) & GENMASK(10, 0)) <= 1); |
| 74 | |
| 75 | return cntpct; |
| 76 | } |
Andre Przywara | 60b7865 | 2018-06-27 01:42:52 +0100 | [diff] [blame] | 77 | #else |
| 78 | /* |
| 79 | * timer_read_counter() using the Arm Generic Timer (aka arch timer). |
| 80 | */ |
| 81 | unsigned long timer_read_counter(void) |
| 82 | { |
| 83 | unsigned long cntpct; |
| 84 | |
| 85 | isb(); |
| 86 | asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); |
| 87 | |
| 88 | return cntpct; |
| 89 | } |
| 90 | #endif |
Aneesh Bansal | d1074b4 | 2015-12-08 13:54:26 +0530 | [diff] [blame] | 91 | |
Simon Glass | e987393 | 2017-04-05 17:53:17 -0600 | [diff] [blame] | 92 | uint64_t get_ticks(void) |
Andre Przywara | de223fd | 2016-11-03 00:56:25 +0000 | [diff] [blame] | 93 | { |
| 94 | unsigned long ticks = timer_read_counter(); |
| 95 | |
| 96 | gd->arch.tbl = ticks; |
| 97 | |
| 98 | return ticks; |
| 99 | } |
| 100 | |
Aneesh Bansal | d1074b4 | 2015-12-08 13:54:26 +0530 | [diff] [blame] | 101 | unsigned long usec2ticks(unsigned long usec) |
| 102 | { |
| 103 | ulong ticks; |
| 104 | if (usec < 1000) |
| 105 | ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; |
| 106 | else |
| 107 | ticks = ((usec / 10) * (get_tbclk() / 100000)); |
| 108 | |
| 109 | return ticks; |
| 110 | } |
Michal Simek | 16d73b9 | 2018-05-15 16:47:02 +0200 | [diff] [blame] | 111 | |
| 112 | ulong timer_get_boot_us(void) |
| 113 | { |
| 114 | u64 val = get_ticks() * 1000000; |
| 115 | |
| 116 | return val / get_tbclk(); |
| 117 | } |