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git01.mediatek.com / filogic / uboot / cc239c72b95765796dba66a36bb15b51369895d6 / . / arch / mips / mach-octeon / include / mach / cvmx-pexp-defs.h
blob: 333c2caee14590c2851e0045a087be14885e943f [file] [log] [blame]
Aaron Williams6aaf6922020-12-11 17:05:43 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Configuration and status register (CSR) definitions for
6 * OCTEON PEXP.
7 */
8
9#ifndef __CVMX_PEXP_DEFS_H__
10#define __CVMX_PEXP_DEFS_H__
11
12#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (0x00011F0000008000ull + ((offset) & 31) * 16)
13#define CVMX_PEXP_NPEI_BIST_STATUS (0x00011F0000008580ull)
14#define CVMX_PEXP_NPEI_BIST_STATUS2 (0x00011F0000008680ull)
15#define CVMX_PEXP_NPEI_CTL_PORT0 (0x00011F0000008250ull)
16#define CVMX_PEXP_NPEI_CTL_PORT1 (0x00011F0000008260ull)
17#define CVMX_PEXP_NPEI_CTL_STATUS (0x00011F0000008570ull)
18#define CVMX_PEXP_NPEI_CTL_STATUS2 (0x00011F000000BC00ull)
19#define CVMX_PEXP_NPEI_DATA_OUT_CNT (0x00011F00000085F0ull)
20#define CVMX_PEXP_NPEI_DBG_DATA (0x00011F0000008510ull)
21#define CVMX_PEXP_NPEI_DBG_SELECT (0x00011F0000008500ull)
22#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (0x00011F00000085C0ull)
23#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (0x00011F00000085D0ull)
24#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (0x00011F0000008450ull + ((offset) & 7) * 16)
25#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (0x00011F00000083B0ull + ((offset) & 7) * 16)
26#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (0x00011F0000008400ull + ((offset) & 7) * 16)
27#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (0x00011F00000084A0ull + ((offset) & 7) * 16)
28#define CVMX_PEXP_NPEI_DMA_CNTS (0x00011F00000085E0ull)
29#define CVMX_PEXP_NPEI_DMA_CONTROL (0x00011F00000083A0ull)
30#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (0x00011F00000085B0ull)
31#define CVMX_PEXP_NPEI_DMA_STATE1 (0x00011F00000086C0ull)
32#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (0x00011F0000008680ull)
33#define CVMX_PEXP_NPEI_DMA_STATE2 (0x00011F00000086D0ull)
34#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (0x00011F0000008690ull)
35#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (0x00011F00000086A0ull)
36#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (0x00011F00000086B0ull)
37#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (0x00011F00000086C0ull)
38#define CVMX_PEXP_NPEI_INT_A_ENB (0x00011F0000008560ull)
39#define CVMX_PEXP_NPEI_INT_A_ENB2 (0x00011F000000BCE0ull)
40#define CVMX_PEXP_NPEI_INT_A_SUM (0x00011F0000008550ull)
41#define CVMX_PEXP_NPEI_INT_ENB (0x00011F0000008540ull)
42#define CVMX_PEXP_NPEI_INT_ENB2 (0x00011F000000BCD0ull)
43#define CVMX_PEXP_NPEI_INT_INFO (0x00011F0000008590ull)
44#define CVMX_PEXP_NPEI_INT_SUM (0x00011F0000008530ull)
45#define CVMX_PEXP_NPEI_INT_SUM2 (0x00011F000000BCC0ull)
46#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (0x00011F0000008600ull)
47#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (0x00011F0000008610ull)
48#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (0x00011F00000084F0ull)
49#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
50 (0x00011F0000008280ull + ((offset) & 31) * 16 - 16 * 12)
51#define CVMX_PEXP_NPEI_MSI_ENB0 (0x00011F000000BC50ull)
52#define CVMX_PEXP_NPEI_MSI_ENB1 (0x00011F000000BC60ull)
53#define CVMX_PEXP_NPEI_MSI_ENB2 (0x00011F000000BC70ull)
54#define CVMX_PEXP_NPEI_MSI_ENB3 (0x00011F000000BC80ull)
55#define CVMX_PEXP_NPEI_MSI_RCV0 (0x00011F000000BC10ull)
56#define CVMX_PEXP_NPEI_MSI_RCV1 (0x00011F000000BC20ull)
57#define CVMX_PEXP_NPEI_MSI_RCV2 (0x00011F000000BC30ull)
58#define CVMX_PEXP_NPEI_MSI_RCV3 (0x00011F000000BC40ull)
59#define CVMX_PEXP_NPEI_MSI_RD_MAP (0x00011F000000BCA0ull)
60#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (0x00011F000000BCF0ull)
61#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (0x00011F000000BD00ull)
62#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (0x00011F000000BD10ull)
63#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (0x00011F000000BD20ull)
64#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (0x00011F000000BD30ull)
65#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (0x00011F000000BD40ull)
66#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (0x00011F000000BD50ull)
67#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (0x00011F000000BD60ull)
68#define CVMX_PEXP_NPEI_MSI_WR_MAP (0x00011F000000BC90ull)
69#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (0x00011F000000BD70ull)
70#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (0x00011F000000BCB0ull)
71#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (0x00011F0000008650ull)
72#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (0x00011F0000008660ull)
73#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (0x00011F0000008670ull)
74#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (0x00011F000000A400ull + ((offset) & 31) * 16)
75#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (0x00011F000000A800ull + ((offset) & 31) * 16)
76#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x00011F000000AC00ull + ((offset) & 31) * 16)
77#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x00011F000000B000ull + ((offset) & 31) * 16)
78#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (0x00011F000000B400ull + ((offset) & 31) * 16)
79#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (0x00011F000000B800ull + ((offset) & 31) * 16)
80#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (0x00011F0000009400ull + ((offset) & 31) * 16)
81#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x00011F0000009800ull + ((offset) & 31) * 16)
82#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x00011F0000009C00ull + ((offset) & 31) * 16)
83#define CVMX_PEXP_NPEI_PKT_CNT_INT (0x00011F0000009110ull)
84#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (0x00011F0000009130ull)
85#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (0x00011F00000090B0ull)
86#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (0x00011F00000090A0ull)
87#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (0x00011F0000009090ull)
88#define CVMX_PEXP_NPEI_PKT_DPADDR (0x00011F0000009080ull)
89#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (0x00011F0000009150ull)
90#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (0x00011F0000009000ull)
91#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (0x00011F0000009190ull)
92#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (0x00011F0000009020ull)
93#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (0x00011F0000009100ull)
94#define CVMX_PEXP_NPEI_PKT_IN_BP (0x00011F00000086B0ull)
95#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (0x00011F000000A000ull + ((offset) & 31) * 16)
96#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (0x00011F00000086A0ull)
97#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (0x00011F00000091A0ull)
98#define CVMX_PEXP_NPEI_PKT_IPTR (0x00011F0000009070ull)
99#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (0x00011F0000009160ull)
100#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (0x00011F00000090D0ull)
101#define CVMX_PEXP_NPEI_PKT_OUT_ENB (0x00011F0000009010ull)
102#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (0x00011F00000090E0ull)
103#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (0x00011F0000008690ull)
104#define CVMX_PEXP_NPEI_PKT_SLIST_ES (0x00011F0000009050ull)
105#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (0x00011F0000009180ull)
106#define CVMX_PEXP_NPEI_PKT_SLIST_NS (0x00011F0000009040ull)
107#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (0x00011F0000009030ull)
108#define CVMX_PEXP_NPEI_PKT_TIME_INT (0x00011F0000009120ull)
109#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (0x00011F0000009140ull)
110#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (0x00011F0000008520ull)
111#define CVMX_PEXP_NPEI_SCRATCH_1 (0x00011F0000008270ull)
112#define CVMX_PEXP_NPEI_STATE1 (0x00011F0000008620ull)
113#define CVMX_PEXP_NPEI_STATE2 (0x00011F0000008630ull)
114#define CVMX_PEXP_NPEI_STATE3 (0x00011F0000008640ull)
115#define CVMX_PEXP_NPEI_WINDOW_CTL (0x00011F0000008380ull)
116#define CVMX_PEXP_NQM_VFX_ACQ(offset) (0x0001450000000030ull + ((offset) & 2047) * 0x20000ull)
117#define CVMX_PEXP_NQM_VFX_AQA(offset) (0x0001450000000024ull + ((offset) & 2047) * 0x20000ull)
118#define CVMX_PEXP_NQM_VFX_ASQ(offset) (0x0001450000000028ull + ((offset) & 2047) * 0x20000ull)
119#define CVMX_PEXP_NQM_VFX_CAP(offset) (0x0001450000000000ull + ((offset) & 2047) * 0x20000ull)
120#define CVMX_PEXP_NQM_VFX_CC(offset) (0x0001450000000014ull + ((offset) & 2047) * 0x20000ull)
121#define CVMX_PEXP_NQM_VFX_CQX_HDBL(offset, block_id) \
122 (0x0001450000001004ull + (((offset) & 31) + ((block_id) & 2047) * 0x4000ull) * 8)
123#define CVMX_PEXP_NQM_VFX_CSTS(offset) (0x000145000000001Cull + ((offset) & 2047) * 0x20000ull)
124#define CVMX_PEXP_NQM_VFX_INTMC(offset) (0x0001450000000010ull + ((offset) & 2047) * 0x20000ull)
125#define CVMX_PEXP_NQM_VFX_INTMS(offset) (0x000145000000000Cull + ((offset) & 2047) * 0x20000ull)
126#define CVMX_PEXP_NQM_VFX_MSIX_PBA(offset) (0x0001450000010200ull + ((offset) & 2047) * 0x20000ull)
127#define CVMX_PEXP_NQM_VFX_NSSR(offset) (0x0001450000000020ull + ((offset) & 2047) * 0x20000ull)
128#define CVMX_PEXP_NQM_VFX_SQX_TDBL(offset, block_id) \
129 (0x0001450000001000ull + (((offset) & 31) + ((block_id) & 2047) * 0x4000ull) * 8)
130#define CVMX_PEXP_NQM_VFX_VECX_MSIX_ADDR(offset, block_id) \
131 (0x0001450000010000ull + (((offset) & 31) + ((block_id) & 2047) * 0x2000ull) * 16)
132#define CVMX_PEXP_NQM_VFX_VECX_MSIX_CTL(offset, block_id) \
133 (0x0001450000010008ull + (((offset) & 31) + ((block_id) & 2047) * 0x2000ull) * 16)
134#define CVMX_PEXP_NQM_VFX_VS(offset) (0x0001450000000008ull + ((offset) & 2047) * 0x20000ull)
135#define CVMX_PEXP_SLITB_MSIXX_TABLE_ADDR(offset) (0x00011F0000004000ull + ((offset) & 127) * 16)
136#define CVMX_PEXP_SLITB_MSIXX_TABLE_DATA(offset) (0x00011F0000004008ull + ((offset) & 127) * 16)
137#define CVMX_PEXP_SLITB_MSIX_MACX_PFX_TABLE_ADDR(offset, block_id) \
138 (0x00011F0000002000ull + ((offset) & 1) * 4096 + ((block_id) & 3) * 0x10ull)
139#define CVMX_PEXP_SLITB_MSIX_MACX_PFX_TABLE_DATA(offset, block_id) \
140 (0x00011F0000002008ull + ((offset) & 1) * 4096 + ((block_id) & 3) * 0x10ull)
141#define CVMX_PEXP_SLITB_PFX_PKT_CNT_INT(offset) (0x00011F0000008000ull + ((offset) & 7) * 16)
142#define CVMX_PEXP_SLITB_PFX_PKT_INT(offset) (0x00011F0000008300ull + ((offset) & 7) * 16)
143#define CVMX_PEXP_SLITB_PFX_PKT_IN_INT(offset) (0x00011F0000008200ull + ((offset) & 7) * 16)
144#define CVMX_PEXP_SLITB_PFX_PKT_RING_RST(offset) (0x00011F0000008400ull + ((offset) & 7) * 16)
145#define CVMX_PEXP_SLITB_PFX_PKT_TIME_INT(offset) (0x00011F0000008100ull + ((offset) & 7) * 16)
146#define CVMX_PEXP_SLITB_PKTX_PF_VF_MBOX_SIGX(offset, block_id) \
147 (0x00011F0000011000ull + (((offset) & 1) + ((block_id) & 127) * 0x4000ull) * 8)
148#define CVMX_PEXP_SLI_BIST_STATUS CVMX_PEXP_SLI_BIST_STATUS_FUNC()
149static inline u64 CVMX_PEXP_SLI_BIST_STATUS_FUNC(void)
150{
151 switch (cvmx_get_octeon_family()) {
152 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
153 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
154 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
155 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
156 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
157 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
158 return 0x00011F0000010580ull;
159 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
160 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
161 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
162 return 0x00011F0000010580ull;
163 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
164 return 0x00011F0000028580ull;
165 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
166 return 0x00011F0000028580ull;
167 }
168 return 0x00011F0000028580ull;
169}
170
171static inline u64 CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset)
172{
173 switch (cvmx_get_octeon_family()) {
174 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
175 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
176 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
177 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
178 return 0x00011F0000010050ull + (offset) * 16;
179 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
180 return 0x00011F0000010050ull + (offset) * 16;
181 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
182 return 0x00011F0000010050ull + (offset) * 16;
183
184 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
185 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
186 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
187 return 0x00011F00000106E0ull + (offset) * 16;
188 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
189 return 0x00011F00000286E0ull + (offset) * 16;
190 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
191 return 0x00011F00000286E0ull + (offset) * 16;
192 }
193 return 0x00011F00000286E0ull + (offset) * 16;
194}
195
196#define CVMX_PEXP_SLI_CTL_STATUS CVMX_PEXP_SLI_CTL_STATUS_FUNC()
197static inline u64 CVMX_PEXP_SLI_CTL_STATUS_FUNC(void)
198{
199 switch (cvmx_get_octeon_family()) {
200 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
201 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
202 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
203 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
204 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
205 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
206 return 0x00011F0000010570ull;
207 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
208 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
209 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
210 return 0x00011F0000010570ull;
211 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
212 return 0x00011F0000028570ull;
213 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
214 return 0x00011F0000028570ull;
215 }
216 return 0x00011F0000028570ull;
217}
218
219#define CVMX_PEXP_SLI_DATA_OUT_CNT CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC()
220static inline u64 CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC(void)
221{
222 switch (cvmx_get_octeon_family()) {
223 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
224 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
225 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
226 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
227 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
228 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
229 return 0x00011F00000105F0ull;
230 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
231 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
232 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
233 return 0x00011F00000105F0ull;
234 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
235 return 0x00011F00000285F0ull;
236 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
237 return 0x00011F00000285F0ull;
238 }
239 return 0x00011F00000285F0ull;
240}
241
242#define CVMX_PEXP_SLI_DBG_DATA (0x00011F0000010310ull)
243#define CVMX_PEXP_SLI_DBG_SELECT (0x00011F0000010300ull)
244static inline u64 CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset)
245{
246 switch (cvmx_get_octeon_family()) {
247 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
248 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
249 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
250 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
251 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
252 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
253 return 0x00011F0000010400ull + (offset) * 16;
254 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
255 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
256 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
257 return 0x00011F0000010400ull + (offset) * 16;
258 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
259 return 0x00011F0000028400ull + (offset) * 16;
260 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
261 return 0x00011F0000028400ull + (offset) * 16;
262 }
263 return 0x00011F0000028400ull + (offset) * 16;
264}
265
266static inline u64 CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset)
267{
268 switch (cvmx_get_octeon_family()) {
269 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
270 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
271 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
272 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
273 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
274 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
275 return 0x00011F00000103E0ull + (offset) * 16;
276 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
277 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
278 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
279 return 0x00011F00000103E0ull + (offset) * 16;
280 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
281 return 0x00011F00000283E0ull + (offset) * 16;
282 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
283 return 0x00011F00000283E0ull + (offset) * 16;
284 }
285 return 0x00011F00000283E0ull + (offset) * 16;
286}
287
288static inline u64 CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset)
289{
290 switch (cvmx_get_octeon_family()) {
291 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
292 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
293 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
294 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
295 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
296 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
297 return 0x00011F0000010420ull + (offset) * 16;
298 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
299 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
300 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
301 return 0x00011F0000010420ull + (offset) * 16;
302 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
303 return 0x00011F0000028420ull + (offset) * 16;
304 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
305 return 0x00011F0000028420ull + (offset) * 16;
306 }
307 return 0x00011F0000028420ull + (offset) * 16;
308}
309
310#define CVMX_PEXP_SLI_INT_ENB_CIU (0x00011F0000013CD0ull)
311#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (0x00011F0000010340ull + ((offset) & 3) * 16)
312#define CVMX_PEXP_SLI_INT_SUM (0x00011F0000010330ull)
313#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (0x00011F0000010600ull)
314#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (0x00011F0000010610ull)
315#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (0x00011F00000106C0ull)
316#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (0x00011F00000106D0ull)
317#define CVMX_PEXP_SLI_MACX_PFX_DMA_VF_INT(offset, block_id) \
318 (0x00011F0000027280ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
319#define CVMX_PEXP_SLI_MACX_PFX_DMA_VF_INT_ENB(offset, block_id) \
320 (0x00011F0000027500ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
321#define CVMX_PEXP_SLI_MACX_PFX_FLR_VF_INT(offset, block_id) \
322 (0x00011F0000027400ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
323#define CVMX_PEXP_SLI_MACX_PFX_INT_ENB(offset, block_id) \
324 (0x00011F0000027080ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
325#define CVMX_PEXP_SLI_MACX_PFX_INT_SUM(offset, block_id) \
326 (0x00011F0000027000ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
327#define CVMX_PEXP_SLI_MACX_PFX_MBOX_INT(offset, block_id) \
328 (0x00011F0000027380ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
329#define CVMX_PEXP_SLI_MACX_PFX_PKT_VF_INT(offset, block_id) \
330 (0x00011F0000027300ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
331#define CVMX_PEXP_SLI_MACX_PFX_PKT_VF_INT_ENB(offset, block_id) \
332 (0x00011F0000027580ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
333#define CVMX_PEXP_SLI_MACX_PFX_PP_VF_INT(offset, block_id) \
334 (0x00011F0000027200ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
335#define CVMX_PEXP_SLI_MACX_PFX_PP_VF_INT_ENB(offset, block_id) \
336 (0x00011F0000027480ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
337#define CVMX_PEXP_SLI_MAC_CREDIT_CNT CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC()
338static inline u64 CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC(void)
339{
340 switch (cvmx_get_octeon_family()) {
341 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
342 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
343 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
344 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
345 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
346 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
347 return 0x00011F0000013D70ull;
348 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
349 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
350 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
351 return 0x00011F0000013D70ull;
352 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
353 return 0x00011F0000023D70ull;
354 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
355 return 0x00011F0000023D70ull;
356 }
357 return 0x00011F0000023D70ull;
358}
359
360#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC()
361static inline u64 CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC(void)
362{
363 switch (cvmx_get_octeon_family()) {
364 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
365 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
366 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
367 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
368 return 0x00011F0000013E10ull;
369 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
370 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
371 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
372 return 0x00011F0000013E10ull;
373 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
374 return 0x00011F0000023E10ull;
375 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
376 return 0x00011F0000023E10ull;
377 }
378 return 0x00011F0000023E10ull;
379}
380
381#define CVMX_PEXP_SLI_MEM_ACCESS_CTL CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC()
382static inline u64 CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC(void)
383{
384 switch (cvmx_get_octeon_family()) {
385 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
386 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
387 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
388 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
389 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
390 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
391 return 0x00011F00000102F0ull;
392 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
393 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
394 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
395 return 0x00011F00000102F0ull;
396 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
397 return 0x00011F00000282F0ull;
398 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
399 return 0x00011F00000282F0ull;
400 }
401 return 0x00011F00000282F0ull;
402}
403
404static inline u64 CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
405{
406 switch (cvmx_get_octeon_family()) {
407 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
408 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
409 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
410 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
411 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
412 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
413 return 0x00011F00000100E0ull + (offset) * 16 - 16 * 12;
414 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
415 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
416 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
417 return 0x00011F00000100E0ull + (offset) * 16 - 16 * 12;
418 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
419 return 0x00011F00000280E0ull + (offset) * 16 - 16 * 12;
420 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
421 return 0x00011F00000280E0ull + (offset) * 16 - 16 * 12;
422 }
423 return 0x00011F00000280E0ull + (offset) * 16 - 16 * 12;
424}
425
426#define CVMX_PEXP_SLI_MEM_CTL CVMX_PEXP_SLI_MEM_CTL_FUNC()
427static inline u64 CVMX_PEXP_SLI_MEM_CTL_FUNC(void)
428{
429 switch (cvmx_get_octeon_family()) {
430 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
431 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
432 return 0x00011F00000105E0ull;
433 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
434 return 0x00011F00000285E0ull;
435 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
436 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
437 return 0x00011F00000285E0ull;
438 }
439 return 0x00011F00000285E0ull;
440}
441
442#define CVMX_PEXP_SLI_MEM_INT_SUM CVMX_PEXP_SLI_MEM_INT_SUM_FUNC()
443static inline u64 CVMX_PEXP_SLI_MEM_INT_SUM_FUNC(void)
444{
445 switch (cvmx_get_octeon_family()) {
446 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
447 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
448 return 0x00011F00000105D0ull;
449 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
450 return 0x00011F00000285D0ull;
451 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
452 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
453 return 0x00011F00000285D0ull;
454 }
455 return 0x00011F00000285D0ull;
456}
457
458static inline u64 CVMX_PEXP_SLI_MSIXX_TABLE_ADDR(unsigned long offset)
459{
460 switch (cvmx_get_octeon_family()) {
461 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
462 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
463 return 0x00011F0000016000ull + (offset) * 16;
464 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
465 return 0x00011F0000000000ull + (offset) * 16;
466 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
467 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
468 return 0x00011F0000000000ull + (offset) * 16;
469 }
470 return 0x00011F0000000000ull + (offset) * 16;
471}
472
473static inline u64 CVMX_PEXP_SLI_MSIXX_TABLE_DATA(unsigned long offset)
474{
475 switch (cvmx_get_octeon_family()) {
476 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
477 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
478 return 0x00011F0000016008ull + (offset) * 16;
479 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
480 return 0x00011F0000000008ull + (offset) * 16;
481 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
482 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
483 return 0x00011F0000000008ull + (offset) * 16;
484 }
485 return 0x00011F0000000008ull + (offset) * 16;
486}
487
488#define CVMX_PEXP_SLI_MSIX_MACX_PF_TABLE_ADDR(offset) (0x00011F0000017C00ull + ((offset) & 3) * 16)
489#define CVMX_PEXP_SLI_MSIX_MACX_PF_TABLE_DATA(offset) (0x00011F0000017C08ull + ((offset) & 3) * 16)
490#define CVMX_PEXP_SLI_MSIX_PBA0 CVMX_PEXP_SLI_MSIX_PBA0_FUNC()
491static inline u64 CVMX_PEXP_SLI_MSIX_PBA0_FUNC(void)
492{
493 switch (cvmx_get_octeon_family()) {
494 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
495 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
496 return 0x00011F0000017000ull;
497 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
498 return 0x00011F0000001000ull;
499 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
500 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
501 return 0x00011F0000001000ull;
502 }
503 return 0x00011F0000001000ull;
504}
505
506#define CVMX_PEXP_SLI_MSIX_PBA1 CVMX_PEXP_SLI_MSIX_PBA1_FUNC()
507static inline u64 CVMX_PEXP_SLI_MSIX_PBA1_FUNC(void)
508{
509 switch (cvmx_get_octeon_family()) {
510 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
511 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
512 return 0x00011F0000017010ull;
513 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
514 return 0x00011F0000001008ull;
515 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
516 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
517 return 0x00011F0000001008ull;
518 }
519 return 0x00011F0000001008ull;
520}
521
522#define CVMX_PEXP_SLI_MSI_ENB0 (0x00011F0000013C50ull)
523#define CVMX_PEXP_SLI_MSI_ENB1 (0x00011F0000013C60ull)
524#define CVMX_PEXP_SLI_MSI_ENB2 (0x00011F0000013C70ull)
525#define CVMX_PEXP_SLI_MSI_ENB3 (0x00011F0000013C80ull)
526#define CVMX_PEXP_SLI_MSI_RCV0 CVMX_PEXP_SLI_MSI_RCV0_FUNC()
527static inline u64 CVMX_PEXP_SLI_MSI_RCV0_FUNC(void)
528{
529 switch (cvmx_get_octeon_family()) {
530 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
531 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
532 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
533 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
534 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
535 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
536 return 0x00011F0000013C10ull;
537 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
538 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
539 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
540 return 0x00011F0000013C10ull;
541 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
542 return 0x00011F0000023C10ull;
543 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
544 return 0x00011F0000023C10ull;
545 }
546 return 0x00011F0000023C10ull;
547}
548
549#define CVMX_PEXP_SLI_MSI_RCV1 CVMX_PEXP_SLI_MSI_RCV1_FUNC()
550static inline u64 CVMX_PEXP_SLI_MSI_RCV1_FUNC(void)
551{
552 switch (cvmx_get_octeon_family()) {
553 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
554 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
555 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
556 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
557 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
558 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
559 return 0x00011F0000013C20ull;
560 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
561 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
562 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
563 return 0x00011F0000013C20ull;
564 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
565 return 0x00011F0000023C20ull;
566 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
567 return 0x00011F0000023C20ull;
568 }
569 return 0x00011F0000023C20ull;
570}
571
572#define CVMX_PEXP_SLI_MSI_RCV2 CVMX_PEXP_SLI_MSI_RCV2_FUNC()
573static inline u64 CVMX_PEXP_SLI_MSI_RCV2_FUNC(void)
574{
575 switch (cvmx_get_octeon_family()) {
576 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
577 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
578 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
579 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
580 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
581 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
582 return 0x00011F0000013C30ull;
583 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
584 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
585 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
586 return 0x00011F0000013C30ull;
587 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
588 return 0x00011F0000023C30ull;
589 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
590 return 0x00011F0000023C30ull;
591 }
592 return 0x00011F0000023C30ull;
593}
594
595#define CVMX_PEXP_SLI_MSI_RCV3 CVMX_PEXP_SLI_MSI_RCV3_FUNC()
596static inline u64 CVMX_PEXP_SLI_MSI_RCV3_FUNC(void)
597{
598 switch (cvmx_get_octeon_family()) {
599 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
600 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
601 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
602 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
603 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
604 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
605 return 0x00011F0000013C40ull;
606 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
607 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
608 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
609 return 0x00011F0000013C40ull;
610 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
611 return 0x00011F0000023C40ull;
612 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
613 return 0x00011F0000023C40ull;
614 }
615 return 0x00011F0000023C40ull;
616}
617
618#define CVMX_PEXP_SLI_MSI_RD_MAP CVMX_PEXP_SLI_MSI_RD_MAP_FUNC()
619static inline u64 CVMX_PEXP_SLI_MSI_RD_MAP_FUNC(void)
620{
621 switch (cvmx_get_octeon_family()) {
622 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
623 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
624 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
625 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
626 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
627 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
628 return 0x00011F0000013CA0ull;
629 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
630 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
631 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
632 return 0x00011F0000013CA0ull;
633 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
634 return 0x00011F0000023CA0ull;
635 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
636 return 0x00011F0000023CA0ull;
637 }
638 return 0x00011F0000023CA0ull;
639}
640
641#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (0x00011F0000013CF0ull)
642#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (0x00011F0000013D00ull)
643#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (0x00011F0000013D10ull)
644#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (0x00011F0000013D20ull)
645#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (0x00011F0000013D30ull)
646#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (0x00011F0000013D40ull)
647#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (0x00011F0000013D50ull)
648#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (0x00011F0000013D60ull)
649#define CVMX_PEXP_SLI_MSI_WR_MAP CVMX_PEXP_SLI_MSI_WR_MAP_FUNC()
650static inline u64 CVMX_PEXP_SLI_MSI_WR_MAP_FUNC(void)
651{
652 switch (cvmx_get_octeon_family()) {
653 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
654 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
655 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
656 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
657 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
658 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
659 return 0x00011F0000013C90ull;
660 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
661 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
662 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
663 return 0x00011F0000013C90ull;
664 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
665 return 0x00011F0000023C90ull;
666 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
667 return 0x00011F0000023C90ull;
668 }
669 return 0x00011F0000023C90ull;
670}
671
672#define CVMX_PEXP_SLI_PCIE_MSI_RCV CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC()
673static inline u64 CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC(void)
674{
675 switch (cvmx_get_octeon_family()) {
676 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
677 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
678 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
679 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
680 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
681 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
682 return 0x00011F0000013CB0ull;
683 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
684 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
685 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
686 return 0x00011F0000013CB0ull;
687 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
688 return 0x00011F0000023CB0ull;
689 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
690 return 0x00011F0000023CB0ull;
691 }
692 return 0x00011F0000023CB0ull;
693}
694
695#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC()
696static inline u64 CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC(void)
697{
698 switch (cvmx_get_octeon_family()) {
699 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
700 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
701 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
702 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
703 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
704 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
705 return 0x00011F0000010650ull;
706 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
707 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
708 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
709 return 0x00011F0000010650ull;
710 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
711 return 0x00011F0000028650ull;
712 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
713 return 0x00011F0000028650ull;
714 }
715 return 0x00011F0000028650ull;
716}
717
718#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC()
719static inline u64 CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC(void)
720{
721 switch (cvmx_get_octeon_family()) {
722 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
723 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
724 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
725 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
726 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
727 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
728 return 0x00011F0000010660ull;
729 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
730 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
731 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
732 return 0x00011F0000010660ull;
733 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
734 return 0x00011F0000028660ull;
735 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
736 return 0x00011F0000028660ull;
737 }
738 return 0x00011F0000028660ull;
739}
740
741#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC()
742static inline u64 CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC(void)
743{
744 switch (cvmx_get_octeon_family()) {
745 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
746 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
747 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
748 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
749 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
750 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
751 return 0x00011F0000010670ull;
752 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
753 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
754 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
755 return 0x00011F0000010670ull;
756 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
757 return 0x00011F0000028670ull;
758 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
759 return 0x00011F0000028670ull;
760 }
761 return 0x00011F0000028670ull;
762}
763
764static inline u64 CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset)
765{
766 switch (cvmx_get_octeon_family()) {
767 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
768 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
769 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
770 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
771 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
772 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
773 return 0x00011F0000012400ull + (offset) * 16;
774
775 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
776 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
777 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
778 return 0x00011F0000012400ull + (offset) * 16;
779 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
780 return 0x00011F00000100B0ull + (offset) * 0x20000ull;
781 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
782 return 0x00011F00000100B0ull + (offset) * 0x20000ull;
783 }
784 return 0x00011F00000100B0ull + (offset) * 0x20000ull;
785}
786
787#define CVMX_PEXP_SLI_PKTX_ERROR_INFO(offset) (0x00011F00000100C0ull + ((offset) & 63) * 0x20000ull)
788static inline u64 CVMX_PEXP_SLI_PKTX_INPUT_CONTROL(unsigned long offset)
789{
790 switch (cvmx_get_octeon_family()) {
791 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
792 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
793 return 0x00011F0000014000ull + (offset) * 16;
794 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
795 return 0x00011F0000010000ull + (offset) * 0x20000ull;
796 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
797 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
798 return 0x00011F0000010000ull + (offset) * 0x20000ull;
799 }
800 return 0x00011F0000010000ull + (offset) * 0x20000ull;
801}
802
803static inline u64 CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset)
804{
805 switch (cvmx_get_octeon_family()) {
806 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
807 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
808 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
809 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
810 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
811 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
812 return 0x00011F0000012800ull + (offset) * 16;
813
814 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
815 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
816 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
817 return 0x00011F0000012800ull + (offset) * 16;
818 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
819 return 0x00011F0000010010ull + (offset) * 0x20000ull;
820 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
821 return 0x00011F0000010010ull + (offset) * 0x20000ull;
822 }
823 return 0x00011F0000010010ull + (offset) * 0x20000ull;
824}
825
826static inline u64 CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
827{
828 switch (cvmx_get_octeon_family()) {
829 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
830 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
831 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
832 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
833 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
834 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
835 return 0x00011F0000012C00ull + (offset) * 16;
836
837 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
838 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
839 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
840 return 0x00011F0000012C00ull + (offset) * 16;
841 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
842 return 0x00011F0000010020ull + (offset) * 0x20000ull;
843 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
844 return 0x00011F0000010020ull + (offset) * 0x20000ull;
845 }
846 return 0x00011F0000010020ull + (offset) * 0x20000ull;
847}
848
849static inline u64 CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
850{
851 switch (cvmx_get_octeon_family()) {
852 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
853 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
854 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
855 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
856 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
857 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
858 return 0x00011F0000013000ull + (offset) * 16;
859
860 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
861 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
862 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
863 return 0x00011F0000013000ull + (offset) * 16;
864 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
865 return 0x00011F0000010030ull + (offset) * 0x20000ull;
866 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
867 return 0x00011F0000010030ull + (offset) * 0x20000ull;
868 }
869 return 0x00011F0000010030ull + (offset) * 0x20000ull;
870}
871
872#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (0x00011F0000013400ull + ((offset) & 31) * 16)
873static inline u64 CVMX_PEXP_SLI_PKTX_INT_LEVELS(unsigned long offset)
874{
875 switch (cvmx_get_octeon_family()) {
876 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
877 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
878 return 0x00011F0000014400ull + (offset) * 16;
879 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
880 return 0x00011F00000100A0ull + (offset) * 0x20000ull;
881 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
882 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
883 return 0x00011F00000100A0ull + (offset) * 0x20000ull;
884 }
885 return 0x00011F00000100A0ull + (offset) * 0x20000ull;
886}
887
888#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (0x00011F0000013800ull + ((offset) & 31) * 16)
889#define CVMX_PEXP_SLI_PKTX_MBOX_INT(offset) (0x00011F0000010210ull + ((offset) & 63) * 0x20000ull)
890static inline u64 CVMX_PEXP_SLI_PKTX_OUTPUT_CONTROL(unsigned long offset)
891{
892 switch (cvmx_get_octeon_family()) {
893 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
894 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
895 return 0x00011F0000014800ull + (offset) * 16;
896 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
897 return 0x00011F0000010050ull + (offset) * 0x20000ull;
898 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
899 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
900 return 0x00011F0000010050ull + (offset) * 0x20000ull;
901 }
902 return 0x00011F0000010050ull + (offset) * 0x20000ull;
903}
904
905static inline u64 CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset)
906{
907 switch (cvmx_get_octeon_family()) {
908 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
909 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
910 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
911 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
912 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
913 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
914 return 0x00011F0000010C00ull + (offset) * 16;
915
916 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
917 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
918 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
919 return 0x00011F0000010C00ull + (offset) * 16;
920 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
921 return 0x00011F0000010060ull + (offset) * 0x20000ull;
922 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
923 return 0x00011F0000010060ull + (offset) * 0x20000ull;
924 }
925 return 0x00011F0000010060ull + (offset) * 0x20000ull;
926}
927
928#define CVMX_PEXP_SLI_PKTX_PF_VF_MBOX_SIGX(offset, block_id) \
929 (0x00011F0000010200ull + (((offset) & 1) + ((block_id) & 63) * 0x4000ull) * 8)
930static inline u64 CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset)
931{
932 switch (cvmx_get_octeon_family()) {
933 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
934 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
935 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
936 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
937 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
938 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
939 return 0x00011F0000011400ull + (offset) * 16;
940
941 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
942 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
943 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
944 return 0x00011F0000011400ull + (offset) * 16;
945 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
946 return 0x00011F0000010070ull + (offset) * 0x20000ull;
947 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
948 return 0x00011F0000010070ull + (offset) * 0x20000ull;
949 }
950 return 0x00011F0000010070ull + (offset) * 0x20000ull;
951}
952
953static inline u64 CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
954{
955 switch (cvmx_get_octeon_family()) {
956 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
957 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
958 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
959 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
960 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
961 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
962 return 0x00011F0000011800ull + (offset) * 16;
963
964 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
965 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
966 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
967 return 0x00011F0000011800ull + (offset) * 16;
968 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
969 return 0x00011F0000010080ull + (offset) * 0x20000ull;
970 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
971 return 0x00011F0000010080ull + (offset) * 0x20000ull;
972 }
973 return 0x00011F0000010080ull + (offset) * 0x20000ull;
974}
975
976static inline u64 CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
977{
978 switch (cvmx_get_octeon_family()) {
979 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
980 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
981 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
982 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
983 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
984 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
985 return 0x00011F0000011C00ull + (offset) * 16;
986
987 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
988 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
989 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
990 return 0x00011F0000011C00ull + (offset) * 16;
991 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
992 return 0x00011F0000010090ull + (offset) * 0x20000ull;
993 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
994 return 0x00011F0000010090ull + (offset) * 0x20000ull;
995 }
996 return 0x00011F0000010090ull + (offset) * 0x20000ull;
997}
998
999#define CVMX_PEXP_SLI_PKTX_VF_INT_SUM(offset) (0x00011F00000100D0ull + ((offset) & 63) * 0x20000ull)
1000#define CVMX_PEXP_SLI_PKTX_VF_SIG(offset) (0x00011F0000014C00ull + ((offset) & 63) * 16)
1001#define CVMX_PEXP_SLI_PKT_BIST_STATUS (0x00011F0000029220ull)
1002#define CVMX_PEXP_SLI_PKT_CNT_INT CVMX_PEXP_SLI_PKT_CNT_INT_FUNC()
1003static inline u64 CVMX_PEXP_SLI_PKT_CNT_INT_FUNC(void)
1004{
1005 switch (cvmx_get_octeon_family()) {
1006 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1007 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1008 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1009 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1010 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1011 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1012 return 0x00011F0000011130ull;
1013 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1014 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1015 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1016 return 0x00011F0000011130ull;
1017 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1018 return 0x00011F0000029130ull;
1019 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1020 return 0x00011F0000029130ull;
1021 }
1022 return 0x00011F0000029130ull;
1023}
1024
1025#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (0x00011F0000011150ull)
1026#define CVMX_PEXP_SLI_PKT_CTL (0x00011F0000011220ull)
1027#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (0x00011F00000110B0ull)
1028#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (0x00011F00000110A0ull)
1029#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (0x00011F0000011090ull)
1030#define CVMX_PEXP_SLI_PKT_DPADDR (0x00011F0000011080ull)
1031#define CVMX_PEXP_SLI_PKT_GBL_CONTROL (0x00011F0000029210ull)
1032#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (0x00011F0000011170ull)
1033#define CVMX_PEXP_SLI_PKT_INSTR_ENB (0x00011F0000011000ull)
1034#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (0x00011F00000111A0ull)
1035#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (0x00011F0000011020ull)
1036#define CVMX_PEXP_SLI_PKT_INT CVMX_PEXP_SLI_PKT_INT_FUNC()
1037static inline u64 CVMX_PEXP_SLI_PKT_INT_FUNC(void)
1038{
1039 switch (cvmx_get_octeon_family()) {
1040 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1041 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1042 return 0x00011F0000011160ull;
1043 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1044 return 0x00011F0000029160ull;
1045 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1046 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1047 return 0x00011F0000029160ull;
1048 }
1049 return 0x00011F0000029160ull;
1050}
1051
1052#define CVMX_PEXP_SLI_PKT_INT_LEVELS (0x00011F0000011120ull)
1053#define CVMX_PEXP_SLI_PKT_IN_BP (0x00011F0000011210ull)
1054static inline u64 CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
1055{
1056 switch (cvmx_get_octeon_family()) {
1057 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1058 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1059 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1060 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1061 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1062 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1063 return 0x00011F0000012000ull + (offset) * 16;
1064
1065 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1066 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1067 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1068 return 0x00011F0000012000ull + (offset) * 16;
1069 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1070 return 0x00011F0000010040ull + (offset) * 0x20000ull;
1071 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1072 return 0x00011F0000010040ull + (offset) * 0x20000ull;
1073 }
1074 return 0x00011F0000010040ull + (offset) * 0x20000ull;
1075}
1076
1077#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC()
1078static inline u64 CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
1079{
1080 switch (cvmx_get_octeon_family()) {
1081 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1082 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1083 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1084 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1085 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1086 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1087 return 0x00011F0000011200ull;
1088 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1089 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1090 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1091 return 0x00011F0000011200ull;
1092 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1093 return 0x00011F0000029200ull;
1094 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1095 return 0x00011F0000029200ull;
1096 }
1097 return 0x00011F0000029200ull;
1098}
1099
1100#define CVMX_PEXP_SLI_PKT_IN_INT CVMX_PEXP_SLI_PKT_IN_INT_FUNC()
1101static inline u64 CVMX_PEXP_SLI_PKT_IN_INT_FUNC(void)
1102{
1103 switch (cvmx_get_octeon_family()) {
1104 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1105 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1106 return 0x00011F0000011150ull;
1107 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1108 return 0x00011F0000029150ull;
1109 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1110 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1111 return 0x00011F0000029150ull;
1112 }
1113 return 0x00011F0000029150ull;
1114}
1115
1116#define CVMX_PEXP_SLI_PKT_IN_JABBER (0x00011F0000029170ull)
1117#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (0x00011F00000111B0ull)
1118#define CVMX_PEXP_SLI_PKT_IPTR (0x00011F0000011070ull)
1119#define CVMX_PEXP_SLI_PKT_MAC0_SIG0 (0x00011F0000011300ull)
1120#define CVMX_PEXP_SLI_PKT_MAC0_SIG1 (0x00011F0000011310ull)
1121#define CVMX_PEXP_SLI_PKT_MAC1_SIG0 (0x00011F0000011320ull)
1122#define CVMX_PEXP_SLI_PKT_MAC1_SIG1 (0x00011F0000011330ull)
1123#define CVMX_PEXP_SLI_PKT_MACX_PFX_RINFO(offset, block_id) \
1124 (0x00011F0000029030ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
1125#define CVMX_PEXP_SLI_PKT_MACX_RINFO(offset) (0x00011F0000011030ull + ((offset) & 3) * 16)
1126#define CVMX_PEXP_SLI_PKT_MEM_CTL CVMX_PEXP_SLI_PKT_MEM_CTL_FUNC()
1127static inline u64 CVMX_PEXP_SLI_PKT_MEM_CTL_FUNC(void)
1128{
1129 switch (cvmx_get_octeon_family()) {
1130 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1131 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1132 return 0x00011F0000011120ull;
1133 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1134 return 0x00011F0000029120ull;
1135 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1136 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1137 return 0x00011F0000029120ull;
1138 }
1139 return 0x00011F0000029120ull;
1140}
1141
1142#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC()
1143static inline u64 CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC(void)
1144{
1145 switch (cvmx_get_octeon_family()) {
1146 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1147 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1148 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1149 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1150 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1151 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1152 return 0x00011F0000011180ull;
1153 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1154 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1155 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1156 return 0x00011F0000011180ull;
1157 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1158 return 0x00011F0000029180ull;
1159 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1160 return 0x00011F0000029180ull;
1161 }
1162 return 0x00011F0000029180ull;
1163}
1164
1165#define CVMX_PEXP_SLI_PKT_OUT_BMODE (0x00011F00000110D0ull)
1166#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (0x00011F0000011240ull)
1167#define CVMX_PEXP_SLI_PKT_OUT_BP_EN2_W1C (0x00011F0000029290ull)
1168#define CVMX_PEXP_SLI_PKT_OUT_BP_EN2_W1S (0x00011F0000029270ull)
1169#define CVMX_PEXP_SLI_PKT_OUT_BP_EN_W1C (0x00011F0000029280ull)
1170#define CVMX_PEXP_SLI_PKT_OUT_BP_EN_W1S (0x00011F0000029260ull)
1171#define CVMX_PEXP_SLI_PKT_OUT_ENB (0x00011F0000011010ull)
1172#define CVMX_PEXP_SLI_PKT_PCIE_PORT (0x00011F00000110E0ull)
1173#define CVMX_PEXP_SLI_PKT_PKIND_VALID (0x00011F0000029190ull)
1174#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (0x00011F00000111F0ull)
1175#define CVMX_PEXP_SLI_PKT_RING_RST CVMX_PEXP_SLI_PKT_RING_RST_FUNC()
1176static inline u64 CVMX_PEXP_SLI_PKT_RING_RST_FUNC(void)
1177{
1178 switch (cvmx_get_octeon_family()) {
1179 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1180 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1181 return 0x00011F00000111E0ull;
1182 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1183 return 0x00011F00000291E0ull;
1184 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1185 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1186 return 0x00011F00000291E0ull;
1187 }
1188 return 0x00011F00000291E0ull;
1189}
1190
1191#define CVMX_PEXP_SLI_PKT_SLIST_ES (0x00011F0000011050ull)
1192#define CVMX_PEXP_SLI_PKT_SLIST_NS (0x00011F0000011040ull)
1193#define CVMX_PEXP_SLI_PKT_SLIST_ROR (0x00011F0000011030ull)
1194#define CVMX_PEXP_SLI_PKT_TIME_INT CVMX_PEXP_SLI_PKT_TIME_INT_FUNC()
1195static inline u64 CVMX_PEXP_SLI_PKT_TIME_INT_FUNC(void)
1196{
1197 switch (cvmx_get_octeon_family()) {
1198 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1199 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1200 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1201 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1202 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1203 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1204 return 0x00011F0000011140ull;
1205 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1206 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1207 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1208 return 0x00011F0000011140ull;
1209 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1210 return 0x00011F0000029140ull;
1211 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1212 return 0x00011F0000029140ull;
1213 }
1214 return 0x00011F0000029140ull;
1215}
1216
1217#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (0x00011F0000011160ull)
1218#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (0x00011F0000010800ull + ((offset) & 31) * 16)
1219static inline u64 CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset)
1220{
1221 switch (cvmx_get_octeon_family()) {
1222 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1223 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1224 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1225 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1226 return 0x00011F0000013D80ull + (offset) * 16;
1227 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1228 return 0x00011F0000013D80ull + (offset) * 16;
1229 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1230 return 0x00011F0000013D80ull + (offset) * 16;
1231 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1232 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1233 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1234 return 0x00011F0000013D80ull + (offset) * 16;
1235 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1236 return 0x00011F0000023D80ull + (offset) * 16;
1237 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1238 return 0x00011F0000023D80ull + (offset) * 16;
1239 }
1240 return 0x00011F0000023D80ull + (offset) * 16;
1241}
1242
1243#define CVMX_PEXP_SLI_SCRATCH_1 CVMX_PEXP_SLI_SCRATCH_1_FUNC()
1244static inline u64 CVMX_PEXP_SLI_SCRATCH_1_FUNC(void)
1245{
1246 switch (cvmx_get_octeon_family()) {
1247 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1248 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1249 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1250 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1251 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1252 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1253 return 0x00011F00000103C0ull;
1254 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1255 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1256 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1257 return 0x00011F00000103C0ull;
1258 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1259 return 0x00011F00000283C0ull;
1260 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1261 return 0x00011F00000283C0ull;
1262 }
1263 return 0x00011F00000283C0ull;
1264}
1265
1266#define CVMX_PEXP_SLI_SCRATCH_2 CVMX_PEXP_SLI_SCRATCH_2_FUNC()
1267static inline u64 CVMX_PEXP_SLI_SCRATCH_2_FUNC(void)
1268{
1269 switch (cvmx_get_octeon_family()) {
1270 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1271 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1272 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1273 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1274 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1275 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1276 return 0x00011F00000103D0ull;
1277 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1278 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1279 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1280 return 0x00011F00000103D0ull;
1281 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1282 return 0x00011F00000283D0ull;
1283 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1284 return 0x00011F00000283D0ull;
1285 }
1286 return 0x00011F00000283D0ull;
1287}
1288
1289#define CVMX_PEXP_SLI_STATE1 CVMX_PEXP_SLI_STATE1_FUNC()
1290static inline u64 CVMX_PEXP_SLI_STATE1_FUNC(void)
1291{
1292 switch (cvmx_get_octeon_family()) {
1293 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1294 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1295 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1296 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1297 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1298 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1299 return 0x00011F0000010620ull;
1300 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1301 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1302 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1303 return 0x00011F0000010620ull;
1304 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1305 return 0x00011F0000028620ull;
1306 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1307 return 0x00011F0000028620ull;
1308 }
1309 return 0x00011F0000028620ull;
1310}
1311
1312#define CVMX_PEXP_SLI_STATE2 CVMX_PEXP_SLI_STATE2_FUNC()
1313static inline u64 CVMX_PEXP_SLI_STATE2_FUNC(void)
1314{
1315 switch (cvmx_get_octeon_family()) {
1316 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1317 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1318 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1319 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1320 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1321 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1322 return 0x00011F0000010630ull;
1323 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1324 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1325 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1326 return 0x00011F0000010630ull;
1327 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1328 return 0x00011F0000028630ull;
1329 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1330 return 0x00011F0000028630ull;
1331 }
1332 return 0x00011F0000028630ull;
1333}
1334
1335#define CVMX_PEXP_SLI_STATE3 CVMX_PEXP_SLI_STATE3_FUNC()
1336static inline u64 CVMX_PEXP_SLI_STATE3_FUNC(void)
1337{
1338 switch (cvmx_get_octeon_family()) {
1339 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1340 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1341 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1342 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1343 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1344 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1345 return 0x00011F0000010640ull;
1346 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1347 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1348 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1349 return 0x00011F0000010640ull;
1350 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1351 return 0x00011F0000028640ull;
1352 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1353 return 0x00011F0000028640ull;
1354 }
1355 return 0x00011F0000028640ull;
1356}
1357
1358#define CVMX_PEXP_SLI_TX_PIPE (0x00011F0000011230ull)
1359#define CVMX_PEXP_SLI_WINDOW_CTL CVMX_PEXP_SLI_WINDOW_CTL_FUNC()
1360static inline u64 CVMX_PEXP_SLI_WINDOW_CTL_FUNC(void)
1361{
1362 switch (cvmx_get_octeon_family()) {
1363 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1364 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1365 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1366 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1367 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1368 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1369 return 0x00011F00000102E0ull;
1370 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1371 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1372 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1373 return 0x00011F00000102E0ull;
1374 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1375 return 0x00011F00000282E0ull;
1376 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1377 return 0x00011F00000282E0ull;
1378 }
1379 return 0x00011F00000282E0ull;
1380}
1381
1382#endif