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git01.mediatek.com / filogic / uboot / cc239c72b95765796dba66a36bb15b51369895d6 / . / arch / arm / mach-sc5xx / Kconfig
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Tom Rinidec7ea02024-05-20 13:35:03 -0600[diff] [blame]1# SPDX-License-Identifier: GPL-2.0-or-later
2#
3# (C) Copyright 2022 - Analog Devices, Inc.
4#
5# Written and/or maintained by Timesys Corporation
6#
7# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
8# Contact: Greg Malysa <greg.malysa@timesys.com>
9#
10
11# All 32-bit platforms require SYS_ARM_CACHE_WRITETHROUGH
12# But it is ignored if selected here, so it must be in the defconfig
13
14if ARCH_SC5XX
15
16config SC57X
17 bool
18 select SUPPORT_SPL
19 select CPU_V7A
20 select PANIC_HANG
21 select COMMON_CLK_ADI_SC57X
22 select TIMER
23 select ADI_SC5XX_TIMER
24
25config SC58X
26 bool
27 select SUPPORT_SPL
28 select CPU_V7A
29 select PANIC_HANG
30 select COMMON_CLK_ADI_SC58X
31 select TIMER
32 select ADI_SC5XX_TIMER
33
34config SC59X
35 bool
36 select SUPPORT_SPL
37 select CPU_V7A
38 select PANIC_HANG
39 select COMMON_CLK_ADI_SC594
40 select TIMER
41 select ADI_SC5XX_TIMER
42 select NOP_PHY
43
44config SC59X_64
45 bool
46 select SUPPORT_SPL
47 select PANIC_HANG
48 select MMC_SDHCI_ADMA_FORCE_32BIT
49 select ARM64
50 select DM
51 select DM_SERIAL
52 select COMMON_CLK_ADI_SC598
53 select GICV3
54 select GIC_600_CLEAR_RDPD
55 select NOP_PHY
56
57config SC_BOOT_MODE
58 int "SC5XX boot mode select"
59 default 1
60 range 0 7
61 help
62 Mode 0: do nothing, just idle
63 Mode 1: boot ldr out of serial flash
64 Mode 7: boot ldr over uart
65
66config SC_BOOT_SPI_BUS
67 int "sc5xx spi boot bus"
68 default 2
69 range 0 4
70 help
71 This is the SPI peripheral number to use for booting, X in the
72 expression `sf probe X:Y`
73
74config SC_BOOT_SPI_SSEL
75 int "sc5xx spi boot chipselect"
76 default 1
77 range 0 6
78 help
79 This is the SPI chip select number to use for booting, Y in the
80 expression `sf probe X:Y`
81
82config SC_BOOT_OSPI_BUS
83 int "sc5xx ospi boot bus"
84 default 0
85 help
86 This is the OSPI peripheral number to use for booting, X in the
87 expression `sf probe X:Y`
88
89config SC_BOOT_OSPI_SSEL
90 int "sc5xx ospi boot chipselect"
91 default 0
92 help
93 This is the OSPI chip select number to use for booting, Y in the
94 expression `sf probe X:Y`
95
96config SYS_FLASH_BASE
97 hex
98 default 0x60000000
99
100config UART_CONSOLE
101 int
102 default 0
103
104config UART4_SERIAL
105 bool
106 depends on DM_SERIAL
107 default y
108
109config WDT_ADI
110 bool
111 default y
112
113config WATCHDOG_TIMEOUT_MSECS
114 int
115 default 30000
116
117config DW_PORTS
118 int
119 default 1
120
121config ADI_BUG_EZKHW21
122 bool "SC584 EZKIT phy bug workaround"
123 depends on SC58X
124 help
125 This workaround affects the SC584 EZKIT and addresses bug EZKHW21.
126 It disables gigabit ethernet mode and limits the board to 100 Mbps
127
128config ADI_CARRIER_SOMCRR_EZKIT
129 bool "Support the EV-SOMCRR-EZKIT"
130 depends on (SC59X || SC59X_64)
131 help
132 Say y to include support for the EV-SOMCRR-EZKIT carrier board,
133 which is compatible with the SC594 and SC598 SOMs. The EZKIT is
134 mutually incompatible with the EZLITE.
135
136config ADI_CARRIER_SOMCRR_EZLITE
137 bool "Support the EV-SOMCRR-EZLITE"
138 depends on (SC59X || SC59X_64)
139 help
140 Say y to include support for the EV-SOMCRR-EZLITE carrier board,
141 which is compatible with the SC594 and SC598 SOMs. The EZLITE is
142 mutually incompatible with the EZKIT.
143
144config ADI_SPL_FORCE_BMODE
145 int "Force the SPL to use this BMODE device during next boot stage"
146 default 0
147 range 0 9
148 depends on SPL
149 help
150 Force the SPL to use this BMODE device during next boot stage.
151 For example, if booting via QSPI, we can force the second stage
152 Of the boot process to use other peripherals via:
153 1 = QSPI -> QSPI
154 5 = QSPI -> OSPI
155 6 = QSPI -> eMMC
156
157config ADI_USE_DMC0
158 bool "Configure DMC0"
159 default y
160 help
161 During hardware initialization, channel 0 of the DMC will be
162 initialized. Select this if you have DMC0 connected to external
163 DDR memory. This is expected to be true for every board using
164 an SC5xx SoC.
165
166config ADI_USE_DMC1
167 bool "Configure DMC1"
168 help
169 During hardware initialization, channel 1 of the DMC will be
170 initialized. Not all processors have a DMC1. Select this if your
171 SoC has DMC1 and you have it connected to external DDR memory.
172
173config ADI_USE_DDR2
174 bool "Configure DMC for DDR2 mode"
175 help
176 Configure the DMC in DDR2 mode. The default is DDR3 and not all
177 parts may actually support DDR2. Please consult the manual for
178 the SoC that you are using to determine if DDR2 mode is supported.
179 This also requires that DDR2 memory is present on the board or it
180 will probably cause strange failure.
181
182menu "Clock configuration"
183
184config CGU0_DF_DIV
185 int "CGU0_DF_DIV"
186 range 0 1
187 help
188 Select 0 to pass CLKIN to PLL
189 Select 1 to pass CLKIN/2 to PLL
190
191config CGU0_VCO_MULT
192 int "CGU0_VCO_MULT"
193 range 0 127
194 help
195 VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL
196 A value of 0 means 128
197
198config CGU0_CCLK_DIV
199 int "CGU0_CCLK_DIV"
200 range 0 31
201 help
202 CCLK_DIV controls the core clock divider
203 A value of 0 means 32
204 CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV
205
206config CGU0_SCLK_DIV
207 int "CGU0_SCLK_DIV"
208 range 0 31
209 help
210 SCLK_DIV controls the system clock divider
211 A value of 0 means 32
212 SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV
213
214config CGU0_SCLK0_DIV
215 int "CGU0_SCLK0_DIV"
216 range 0 7
217 help
218 A value of 0 means 8
219 SCLK0 = SCLK / SCLK0_DIV
220
221config CGU0_SCLK1_DIV
222 int "CGU0_SCLK1_DIV"
223 depends on (SC57X || SC58X)
224 range 0 7
225 help
226 A value of 0 means 8
227 SCLK1 = SCLK / SCLK1_DIV
228
229config CGU0_DCLK_DIV
230 int "CGU0_DCLK_DIV"
231 range 0 31
232 help
233 DCLK_DIV controls the DDR clock divider
234 A value of 0 means 32
235 DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV
236
237config CGU0_OCLK_DIV
238 int "CGU0_OCLK_DIV"
239 range 0 127
240 help
241 OCLK_DIV controls the output clock divider
242 A value of 0 means 128
243 OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV
244
245config CGU0_DIV_S1SELEX
246 int "CGU0_DIV_S1SELEX"
247 depends on !SC57X && !SC58X
248 range 0 255
249 help
250 CGU0 SCLK1 Extended divisor register.
251 A value of 0 means 256.
252 SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX
253
254config CGU0_CLKOUTSEL
255 int "CGU0_CLKOUTSEL"
256 default 0
257 range 0 31
258 help
259 Select signal driven through CLKOUT pin multiplexer.
260 This value varies on each SOC. Refer to
261 CGU_CLKOUTSEL.CLKOUTSEL in the Hardware Reference Manual
262 for values applicable to each SOC.
263 Commonly, values 0 and 1 select CLKIN0 or CLKIN1 respectively.
264
265config CGU1_PLL3_DDRCLK
266 bool "DDRCLK From 3rd PLL"
267 depends on SC59X_64
268 help
269 3rd PLL output is connected to DMC block when set.
270 When cleared, DDR clock is CLKO3 output of CDU.
271
272config CGU1_PLL3_VCO_MSEL
273 int "CGU0_PLL3_VCO_MSEL"
274 depends on CGU1_PLL3_DDRCLK
275 range 1 128
276 help
277 PLL multiplier value for the 3rd PLL.
278 DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV
279
280config CGU1_PLL3_DCLK_DIV
281 int "CGU0_PLL3_DCLK_DIV"
282 depends on CGU1_PLL3_DDRCLK
283 range 1 32
284 help
285 PLL divider value for the 3rd PLL.
286 DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV
287
288config CGU1_DF_DIV
289 int "CGU1_DF_DIV"
290 range 0 1
291 help
292 Select 0 to pass CLKIN to PLL
293 Select 1 to pass CLKIN/2 to PLL
294
295config CGU1_VCO_MULT
296 int "CGU1_VCO_MULT"
297 range 0 127
298 help
299 VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL
300 A value of 0 means 128
301
302config CGU1_CCLK_DIV
303 int "CGU1_CCLK_DIV"
304 range 0 31
305 help
306 CCLK_DIV controls the core clock divider
307 A value of 0 means 32
308 CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV
309
310config CGU1_SCLK_DIV
311 int "CGU1_SCLK_DIV"
312 range 0 31
313 help
314 SCLK_DIV controls the system clock divider
315 A value of 0 means 32
316 SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV
317
318config CGU1_SCLK0_DIV
319 int "CGU1_SCLK0_DIV"
320 depends on (SC57X || SC58X || SC59X)
321 range 0 7
322 help
323 A value of 0 means 8
324 SCLK0 = SCLK / SCLK0_DIV
325
326config CGU1_SCLK1_DIV
327 int "CGU1_SCLK1_DIV"
328 depends on (SC57X || SC58X)
329 range 0 7
330 help
331 A value of 0 means 8
332 SCLK1 = SCLK / SCLK1_DIV
333
334config CGU1_DCLK_DIV
335 int "CGU1_DCLK_DIV"
336 range 0 31
337 help
338 DCLK_DIV controls the DDR clock divider
339 A value of 0 means 32
340 DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV
341
342config CGU1_OCLK_DIV
343 int "CGU1_OCLK_DIV"
344 range 0 127
345 help
346 OCLK_DIV controls the output clock divider
347 A value of 0 means 128
348 OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV
349
350config CGU1_DIV_S0SELEX
351 int "CGU1_DIV_S0SELEX"
352 depends on !SC57X && !SC58X && !SC59X
353 range 0 255
354 help
355 CGU1 SCLK0 Extended divisor register.
356 A value of 0 means 256.
357 SCLK0 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S0SELEX
358
359config CGU1_DIV_S1SELEX
360 int "CGU1_DIV_S1SELEX"
361 depends on !SC57X && !SC58X
362 range 0 255
363 help
364 CGU1 SCLK1 Extended divisor register.
365 A value of 0 means 256.
366 SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX
367
368config CDU0_CGU1_CLKIN
369 int "CDU0 CGU1 CLKINn Select"
370 default 0
371 range 0 1
372 help
373 Selects source clock for CGU1.
374 0 for CLKIN0
375 1 for CLKIN1
376
377config CDU0_CLKO0
378 int "CDU0_CLKO0"
379 range 1 7
380 help
381 Clock source select. Refer to SOC Hardware Reference Manual
382
383config CDU0_CLKO1
384 int "CDU0_CLKO1"
385 range 1 7
386 help
387 Clock source select. Refer to SOC Hardware Reference Manual
388
389config CDU0_CLKO2
390 int "CDU0_CLKO2"
391 range 1 7
392 help
393 Clock source select. Refer to SOC Hardware Reference Manual
394
395config CDU0_CLKO3
396 int "CDU0_CLKO3"
397 range 1 7
398 help
399 Clock source select. Refer to SOC Hardware Reference Manual
400
401config CDU0_CLKO4
402 int "CDU0_CLKO4"
403 range 1 7
404 help
405 Clock source select. Refer to SOC Hardware Reference Manual
406
407config CDU0_CLKO5
408 int "CDU0_CLKO5"
409 range 1 7
410 help
411 Clock source select. Refer to SOC Hardware Reference Manual
412
413config CDU0_CLKO6
414 int "CDU0_CLKO6"
415 range 1 7
416 help
417 Clock source select. Refer to SOC Hardware Reference Manual
418
419config CDU0_CLKO7
420 int "CDU0_CLKO7"
421 range 1 7
422 help
423 Clock source select. Refer to SOC Hardware Reference Manual
424
425config CDU0_CLKO8
426 int "CDU0_CLKO8"
427 range 1 7
428 help
429 Clock source select. Refer to SOC Hardware Reference Manual
430
431config CDU0_CLKO9
432 int "CDU0_CLKO9"
433 range 1 7
434 help
435 Clock source select. Refer to SOC Hardware Reference Manual
436
437config CDU0_CLKO10
438 int "CDU0_CLKO10"
439 range 1 7
440 depends on (SC59X || SC59X_64)
441 help
442 Clock source select. Refer to SOC Hardware Reference Manual
443
444config CDU0_CLKO12
445 int "CDU0_CLKO12"
446 range 1 7
447 depends on (SC59X || SC59X_64)
448 help
449 Clock source select. Refer to SOC Hardware Reference Manual
450
451config CDU0_CLKO13
452 int "CDU0_CLKO13"
453 range 1 7
454 depends on SC59X_64
455 help
456 Clock source select. Refer to SOC Hardware Reference Manual
457
458config CDU0_CLKO14
459 int "CDU0_CLKO14"
460 range 1 7
461 depends on SC59X_64
462 help
463 Clock source select. Refer to SOC Hardware Reference Manual
464
465endmenu
466
467config ADI_GPIO
468 bool
469 default y
470
471config PINCTRL_ADI
472 bool
473 default y
474
475endif