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git01.mediatek.com / filogic / uboot / cc18580966244a82ff6ee5754e7000be7384bda1 / . / arch / sandbox / dts / test.dts
blob: c25614ab8806aef6b908a5f616d2dd47492fe528 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
7 #size-cells = <0>;
8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
12 eth5 = &eth_5;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]13 i2c0 = "/i2c@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]14 pci0 = &pci;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]15 rtc0 = &rtc_0;
16 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]17 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]18 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]19 testbus3 = "/some-bus";
20 testfdt0 = "/some-bus/c-test@0";
21 testfdt1 = "/some-bus/c-test@1";
22 testfdt3 = "/b-test";
23 testfdt5 = "/some-bus/c-test@5";
24 testfdt8 = "/a-test";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]25 usb0 = &usb_0;
26 usb1 = &usb_1;
27 usb2 = &usb_2;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]28 };
29
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]30 a-test {
31 reg = <0>;
32 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]33 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]34 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]35 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]36 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
37 <0>, <&gpio_a 12>;
38 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
39 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
40 <&gpio_b 9 0xc 3 2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]41 };
42
43 junk {
44 reg = <1>;
45 compatible = "not,compatible";
46 };
47
48 no-compatible {
49 reg = <2>;
50 };
51
52 b-test {
53 reg = <3>;
54 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]55 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]56 ping-add = <3>;
57 };
58
59 some-bus {
60 #address-cells = <1>;
61 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]62 compatible = "denx,u-boot-test-bus";
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]63 reg = <3>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]64 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]65 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]66 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]67 compatible = "denx,u-boot-fdt-test";
68 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]69 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]70 ping-add = <5>;
71 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]72 c-test@0 {
73 compatible = "denx,u-boot-fdt-test";
74 reg = <0>;
75 ping-expect = <6>;
76 ping-add = <6>;
77 };
78 c-test@1 {
79 compatible = "denx,u-boot-fdt-test";
80 reg = <1>;
81 ping-expect = <7>;
82 ping-add = <7>;
83 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]84 };
85
86 d-test {
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]87 reg = <3>;
88 ping-expect = <6>;
89 ping-add = <6>;
90 compatible = "google,another-fdt-test";
91 };
92
93 e-test {
94 reg = <3>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]95 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]96 ping-add = <6>;
97 compatible = "google,another-fdt-test";
98 };
99
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]100 f-test {
101 compatible = "denx,u-boot-fdt-test";
102 };
103
104 g-test {
105 compatible = "denx,u-boot-fdt-test";
106 };
107
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]108 eth@10002000 {
109 compatible = "sandbox,eth";
110 reg = <0x10002000 0x1000>;
111 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
112 };
113
114 eth_5: eth@10003000 {
115 compatible = "sandbox,eth";
116 reg = <0x10003000 0x1000>;
117 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
118 };
119
120 eth@10004000 {
121 compatible = "sandbox,eth";
122 reg = <0x10004000 0x1000>;
123 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
124 };
125
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]126 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]127 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]128 gpio-controller;
129 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]130 gpio-bank-name = "a";
131 num-gpios = <20>;
132 };
133
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]134 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]135 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]136 gpio-controller;
137 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]138 gpio-bank-name = "b";
139 num-gpios = <10>;
140 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]141
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]142 i2c@0 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 reg = <0>;
146 compatible = "sandbox,i2c";
147 clock-frequency = <100000>;
148 eeprom@2c {
149 reg = <0x2c>;
150 compatible = "i2c-eeprom";
151 emul {
152 compatible = "sandbox,i2c-eeprom";
153 sandbox,filename = "i2c.bin";
154 sandbox,size = <256>;
155 };
156 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]157
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]158 rtc_0: rtc@43 {
159 reg = <0x43>;
160 compatible = "sandbox-rtc";
161 emul {
162 compatible = "sandbox,i2c-rtc";
163 };
164 };
165
166 rtc_1: rtc@61 {
167 reg = <0x61>;
168 compatible = "sandbox-rtc";
169 emul {
170 compatible = "sandbox,i2c-rtc";
171 };
172 };
173
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]174 sandbox_pmic: sandbox_pmic {
175 reg = <0x40>;
176 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]177 };
178
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]179 pci: pci-controller {
180 compatible = "sandbox,pci";
181 device_type = "pci";
182 #address-cells = <3>;
183 #size-cells = <2>;
184 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
185 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
186 pci@1f,0 {
187 compatible = "pci-generic";
188 reg = <0xf800 0 0 0 0>;
189 emul@1f,0 {
190 compatible = "sandbox,swap-case";
191 };
192 };
193 };
194
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]195 spi@0 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 reg = <0>;
199 compatible = "sandbox,spi";
200 cs-gpios = <0>, <&gpio_a 0>;
201 spi.bin@0 {
202 reg = <0>;
203 compatible = "spansion,m25p16", "spi-flash";
204 spi-max-frequency = <40000000>;
205 sandbox,filename = "spi.bin";
206 };
207 };
208
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]209 uart0: serial {
210 compatible = "sandbox,serial";
211 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]212 };
213
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]214 usb_0: usb@0 {
215 compatible = "sandbox,usb";
216 status = "disabled";
217 hub {
218 compatible = "sandbox,usb-hub";
219 #address-cells = <1>;
220 #size-cells = <0>;
221 flash-stick {
222 reg = <0>;
223 compatible = "sandbox,usb-flash";
224 };
225 };
226 };
227
228 usb_1: usb@1 {
229 compatible = "sandbox,usb";
230 hub {
231 compatible = "usb-hub";
232 usb,device-class = <9>;
233 hub-emul {
234 compatible = "sandbox,usb-hub";
235 #address-cells = <1>;
236 #size-cells = <0>;
237 flash-stick {
238 reg = <0>;
239 compatible = "sandbox,usb-flash";
240 sandbox,filepath = "testflash.bin";
241 };
242
243 };
244 };
245 };
246
247 usb_2: usb@2 {
248 compatible = "sandbox,usb";
249 status = "disabled";
250 };
251
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]252};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]253
254#include "sandbox_pmic.dtsi"