Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 |
| 3 | * |
| 4 | * Authors: Nick.Spence@freescale.com |
| 5 | * Wilson.Lo@freescale.com |
| 6 | * scottwood@freescale.com |
| 7 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <mpc83xx.h> |
| 13 | #include <spd_sdram.h> |
| 14 | |
| 15 | #include <asm/bitops.h> |
| 16 | #include <asm/io.h> |
| 17 | |
| 18 | #include <asm/processor.h> |
| 19 | |
Wolfgang Denk | d112a2c | 2007-09-15 20:48:41 +0200 | [diff] [blame] | 20 | DECLARE_GLOBAL_DATA_PTR; |
| 21 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 22 | #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 23 | static void resume_from_sleep(void) |
| 24 | { |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 25 | u32 magic = *(u32 *)0; |
| 26 | |
| 27 | typedef void (*func_t)(void); |
| 28 | func_t resume = *(func_t *)4; |
| 29 | |
| 30 | if (magic == 0xf5153ae5) |
| 31 | resume(); |
| 32 | |
| 33 | gd->flags &= ~GD_FLG_SILENT; |
| 34 | puts("\nResume from sleep failed: bad magic word\n"); |
| 35 | } |
| 36 | #endif |
| 37 | |
| 38 | /* Fixed sdram init -- doesn't use serial presence detect. |
| 39 | * |
| 40 | * This is useful for faster booting in configs where the RAM is unlikely |
| 41 | * to be changed, or for things like NAND booting where space is tight. |
| 42 | */ |
| 43 | static long fixed_sdram(void) |
| 44 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 45 | u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 46 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | #ifndef CONFIG_SYS_RAMBOOT |
| 48 | volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 49 | u32 msize_log2 = __ilog2(msize); |
| 50 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 51 | im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 52 | im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 53 | im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 54 | |
| 55 | /* |
| 56 | * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], |
| 57 | * or the DDR2 controller may fail to initialize correctly. |
| 58 | */ |
Ingo van Lil | f0f778a | 2009-11-24 14:09:21 +0100 | [diff] [blame] | 59 | __udelay(50000); |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 60 | |
Joe Hershberger | 5ade390 | 2011-10-11 23:57:31 -0500 | [diff] [blame] | 61 | #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) |
| 62 | #warning Chip select bounds is only configurable in 16MB increments |
| 63 | #endif |
| 64 | im->ddr.csbnds[0].csbnds = |
| 65 | ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | |
| 66 | (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & |
| 67 | CSBNDS_EA); |
| 68 | im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 69 | |
| 70 | /* Currently we use only one CS, so disable the other bank. */ |
| 71 | im->ddr.cs_config[1] = 0; |
| 72 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 73 | im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; |
| 74 | im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
| 75 | im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 76 | im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
| 77 | im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 78 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 80 | if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 81 | im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 82 | else |
| 83 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 85 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 86 | im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2; |
| 87 | im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; |
| 88 | im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 89 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 90 | im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 91 | sync(); |
| 92 | |
| 93 | /* enable DDR controller */ |
| 94 | im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 95 | #endif |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 96 | |
| 97 | return msize; |
| 98 | } |
| 99 | |
Becky Bruce | bd99ae7 | 2008-06-09 16:03:40 -0500 | [diff] [blame] | 100 | phys_size_t initdram(int board_type) |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 101 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 103 | volatile fsl_lbc_t *lbc = &im->im_lbc; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 104 | u32 msize; |
| 105 | |
| 106 | if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
| 107 | return -1; |
| 108 | |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 109 | /* DDR SDRAM - Main SODIMM */ |
| 110 | msize = fixed_sdram(); |
| 111 | |
| 112 | /* Local Bus setup lbcr and mrtpr */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 113 | lbc->lbcr = CONFIG_SYS_LBC_LBCR; |
| 114 | lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 115 | sync(); |
| 116 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 117 | #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 118 | if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) |
| 119 | resume_from_sleep(); |
| 120 | #endif |
| 121 | |
Scott Wood | 865b8ae | 2007-04-16 14:54:15 -0500 | [diff] [blame] | 122 | /* return total bus SDRAM size(bytes) -- DDR */ |
| 123 | return msize; |
| 124 | } |