| developer | a4bb22b | 2022-05-20 11:21:34 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * MT regs definitions, follows on from mipsregs.h |
| 4 | * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved. |
| 5 | * Elizabeth Clarke et. al. |
| 6 | * |
| 7 | */ |
| 8 | #ifndef _ASM_MIPSMTREGS_H |
| 9 | #define _ASM_MIPSMTREGS_H |
| 10 | |
| 11 | #include <asm/mipsregs.h> |
| 12 | |
| 13 | /* |
| 14 | * Macros for use in assembly language code |
| 15 | */ |
| 16 | |
| 17 | #define CP0_MVPCONTROL $0, 1 |
| 18 | #define CP0_MVPCONF0 $0, 2 |
| 19 | #define CP0_MVPCONF1 $0, 3 |
| 20 | #define CP0_VPECONTROL $1, 1 |
| 21 | #define CP0_VPECONF0 $1, 2 |
| 22 | #define CP0_VPECONF1 $1, 3 |
| 23 | #define CP0_YQMASK $1, 4 |
| 24 | #define CP0_VPESCHEDULE $1, 5 |
| 25 | #define CP0_VPESCHEFBK $1, 6 |
| 26 | #define CP0_TCSTATUS $2, 1 |
| 27 | #define CP0_TCBIND $2, 2 |
| 28 | #define CP0_TCRESTART $2, 3 |
| 29 | #define CP0_TCHALT $2, 4 |
| 30 | #define CP0_TCCONTEXT $2, 5 |
| 31 | #define CP0_TCSCHEDULE $2, 6 |
| 32 | #define CP0_TCSCHEFBK $2, 7 |
| 33 | #define CP0_SRSCONF0 $6, 1 |
| 34 | #define CP0_SRSCONF1 $6, 2 |
| 35 | #define CP0_SRSCONF2 $6, 3 |
| 36 | #define CP0_SRSCONF3 $6, 4 |
| 37 | #define CP0_SRSCONF4 $6, 5 |
| 38 | |
| 39 | /* MVPControl fields */ |
| 40 | #define MVPCONTROL_EVP (_ULCAST_(1)) |
| 41 | |
| 42 | #define MVPCONTROL_VPC_SHIFT 1 |
| 43 | #define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT) |
| 44 | |
| 45 | #define MVPCONTROL_STLB_SHIFT 2 |
| 46 | #define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) |
| 47 | |
| 48 | /* MVPConf0 fields */ |
| 49 | #define MVPCONF0_PTC_SHIFT 0 |
| 50 | #define MVPCONF0_PTC (_ULCAST_(0xff)) |
| 51 | #define MVPCONF0_PVPE_SHIFT 10 |
| 52 | #define MVPCONF0_PVPE (_ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT) |
| 53 | #define MVPCONF0_TCA_SHIFT 15 |
| 54 | #define MVPCONF0_TCA (_ULCAST_(1) << MVPCONF0_TCA_SHIFT) |
| 55 | #define MVPCONF0_PTLBE_SHIFT 16 |
| 56 | #define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT) |
| 57 | #define MVPCONF0_TLBS_SHIFT 29 |
| 58 | #define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT) |
| 59 | #define MVPCONF0_M_SHIFT 31 |
| 60 | #define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT) |
| 61 | |
| 62 | /* config3 fields */ |
| 63 | #define CONFIG3_MT_SHIFT 2 |
| 64 | #define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT) |
| 65 | |
| 66 | /* VPEControl fields (per VPE) */ |
| 67 | #define VPECONTROL_TARGTC (_ULCAST_(0xff)) |
| 68 | |
| 69 | #define VPECONTROL_TE_SHIFT 15 |
| 70 | #define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT) |
| 71 | #define VPECONTROL_EXCPT_SHIFT 16 |
| 72 | #define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT) |
| 73 | |
| 74 | /* Thread Exception Codes for EXCPT field */ |
| 75 | #define THREX_TU 0 |
| 76 | #define THREX_TO 1 |
| 77 | #define THREX_IYQ 2 |
| 78 | #define THREX_GSX 3 |
| 79 | #define THREX_YSCH 4 |
| 80 | #define THREX_GSSCH 5 |
| 81 | |
| 82 | #define VPECONTROL_GSI_SHIFT 20 |
| 83 | #define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT) |
| 84 | #define VPECONTROL_YSI_SHIFT 21 |
| 85 | #define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT) |
| 86 | |
| 87 | /* VPEConf0 fields (per VPE) */ |
| 88 | #define VPECONF0_VPA_SHIFT 0 |
| 89 | #define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT) |
| 90 | #define VPECONF0_MVP_SHIFT 1 |
| 91 | #define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT) |
| 92 | #define VPECONF0_XTC_SHIFT 21 |
| 93 | #define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) |
| 94 | |
| 95 | /* VPEConf1 fields (per VPE) */ |
| 96 | #define VPECONF1_NCP1_SHIFT 0 |
| 97 | #define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT) |
| 98 | #define VPECONF1_NCP2_SHIFT 10 |
| 99 | #define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT) |
| 100 | #define VPECONF1_NCX_SHIFT 20 |
| 101 | #define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT) |
| 102 | |
| 103 | /* TCStatus fields (per TC) */ |
| 104 | #define TCSTATUS_TASID (_ULCAST_(0xff)) |
| 105 | #define TCSTATUS_IXMT_SHIFT 10 |
| 106 | #define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT) |
| 107 | #define TCSTATUS_TKSU_SHIFT 11 |
| 108 | #define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT) |
| 109 | #define TCSTATUS_A_SHIFT 13 |
| 110 | #define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT) |
| 111 | #define TCSTATUS_DA_SHIFT 15 |
| 112 | #define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT) |
| 113 | #define TCSTATUS_DT_SHIFT 20 |
| 114 | #define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT) |
| 115 | #define TCSTATUS_TDS_SHIFT 21 |
| 116 | #define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT) |
| 117 | #define TCSTATUS_TSST_SHIFT 22 |
| 118 | #define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT) |
| 119 | #define TCSTATUS_RNST_SHIFT 23 |
| 120 | #define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT) |
| 121 | /* Codes for RNST */ |
| 122 | #define TC_RUNNING 0 |
| 123 | #define TC_WAITING 1 |
| 124 | #define TC_YIELDING 2 |
| 125 | #define TC_GATED 3 |
| 126 | |
| 127 | #define TCSTATUS_TMX_SHIFT 27 |
| 128 | #define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT) |
| 129 | /* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */ |
| 130 | |
| 131 | /* TCBind */ |
| 132 | #define TCBIND_CURVPE_SHIFT 0 |
| 133 | #define TCBIND_CURVPE (_ULCAST_(0xf)) |
| 134 | |
| 135 | #define TCBIND_CURTC_SHIFT 21 |
| 136 | |
| 137 | #define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT) |
| 138 | |
| 139 | /* TCHalt */ |
| 140 | #define TCHALT_H (_ULCAST_(1)) |
| 141 | |
| 142 | #endif |