Jaehoon Chung | e3fb6fa | 2014-05-16 13:59:51 +0900 | [diff] [blame] | 1 | * Exynos DWC_mobile_storage |
Amar | 070e83f | 2013-04-27 11:42:53 +0530 | [diff] [blame] | 2 | |
Jaehoon Chung | e3fb6fa | 2014-05-16 13:59:51 +0900 | [diff] [blame] | 3 | The Exynos provides DWC_mobile_storage interface which supports |
Amar | 070e83f | 2013-04-27 11:42:53 +0530 | [diff] [blame] | 4 | . Embedded Multimedia Cards (EMMC-version 4.5) |
| 5 | . Secure Digital memory (SD mem-version 2.0) |
| 6 | . Secure Digital I/O (SDIO-version 3.0) |
| 7 | . Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1) |
| 8 | |
Jaehoon Chung | e3fb6fa | 2014-05-16 13:59:51 +0900 | [diff] [blame] | 9 | The Exynos DWC_mobile_storage provides four channels. |
Amar | 070e83f | 2013-04-27 11:42:53 +0530 | [diff] [blame] | 10 | SOC specific and Board specific properties are channel specific. |
| 11 | |
| 12 | Required SoC Specific Properties: |
| 13 | |
| 14 | - compatible: should be |
Sam Protsenko | 4c6b4ae | 2024-08-07 22:14:21 -0500 | [diff] [blame] | 15 | - samsung,exynos4412-dw-mshc: for Exynos4 platforms |
| 16 | - samsung,exynos-dwmmc: for Exynos5 platforms |
| 17 | - samsung,exynos7-dw-mshc-smu: for Exynos7 platforms (with SMU block) |
Amar | 070e83f | 2013-04-27 11:42:53 +0530 | [diff] [blame] | 18 | |
| 19 | - reg: physical base address of the controller and length of memory mapped |
| 20 | region. |
| 21 | |
| 22 | - interrupts: The interrupt number to the cpu. |
| 23 | |
| 24 | Required Board Specific Properties: |
| 25 | |
| 26 | - #address-cells: should be 1. |
| 27 | - #size-cells: should be 0. |
Sam Protsenko | 4c6b4ae | 2024-08-07 22:14:21 -0500 | [diff] [blame] | 28 | - bus-width: The width of the bus used to interface the devices |
Amar | 070e83f | 2013-04-27 11:42:53 +0530 | [diff] [blame] | 29 | supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO). |
| 30 | . Typically the bus width is 4 or 8. |
Sam Protsenko | 4c6b4ae | 2024-08-07 22:14:21 -0500 | [diff] [blame] | 31 | - samsung,dw-mshc-ciu-div: The divider value for the card interface unit (ciu) |
| 32 | clock (0..7). |
| 33 | - samsung,dw-mshc-sdr-timing: The timing values for single data rate (SDR) mode |
| 34 | operation. |
| 35 | . First value is CIU clock phase shift value for TX mode (0..7). |
| 36 | . Second value is CIU clock phase shift value for RX mode (0..7). |
| 37 | - samsung,dw-mshc-ddr-timing: The timing values for double data rate (DDR) mode |
| 38 | operation. If missing, values from samsung,dw-mshc-sdr-timing are used. |
| 39 | . First value is CIU clock phase shift value for TX mode (0..7). |
| 40 | . Second value is CIU clock phase shift value for RX mode (0..7). |
Amar | 070e83f | 2013-04-27 11:42:53 +0530 | [diff] [blame] | 41 | |
| 42 | Example: |
| 43 | |
| 44 | mmc@12200000 { |
Sam Protsenko | 4c6b4ae | 2024-08-07 22:14:21 -0500 | [diff] [blame] | 45 | bus-width = <8>; |
| 46 | non-removable; |
| 47 | samsung,dw-mshc-ciu-div = <3>; |
| 48 | samsung,dw-mshc-sdr-timing = <1 3>; |
| 49 | samsung,dw-mshc-ddr-timing = <0 2>; |
| 50 | }; |
| 51 | |
Amar | 070e83f | 2013-04-27 11:42:53 +0530 | [diff] [blame] | 52 | In the above example, |
| 53 | . The bus width is 8 |
Sam Protsenko | 4c6b4ae | 2024-08-07 22:14:21 -0500 | [diff] [blame] | 54 | . Divider value for CLKSEL register is 3. The CIU clock rate will be |
| 55 | calculated as SDCLKIN / (3 + 1). |
| 56 | . SDR and DDR timings are comprised of 2 values as explained below |
Amar | 070e83f | 2013-04-27 11:42:53 +0530 | [diff] [blame] | 57 | 1 - SelClk_sample |
| 58 | 3 - SelClk_drv |
Sam Protsenko | 4c6b4ae | 2024-08-07 22:14:21 -0500 | [diff] [blame] | 59 | . The 'non-removable' flag indicates whether the particular device |
Amar | 070e83f | 2013-04-27 11:42:53 +0530 | [diff] [blame] | 60 | cannot be removed (always present) or it is a removable device. |
Sam Protsenko | 4c6b4ae | 2024-08-07 22:14:21 -0500 | [diff] [blame] | 61 | Flag is present - Indicates that the device cannot be removed. |
| 62 | Flag is not present - Indicates that the device is removable. |