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Jaehoon Chunge3fb6fa2014-05-16 13:59:51 +09001* Exynos DWC_mobile_storage
Amar070e83f2013-04-27 11:42:53 +05302
Jaehoon Chunge3fb6fa2014-05-16 13:59:51 +09003The Exynos provides DWC_mobile_storage interface which supports
Amar070e83f2013-04-27 11:42:53 +05304. Embedded Multimedia Cards (EMMC-version 4.5)
5. Secure Digital memory (SD mem-version 2.0)
6. Secure Digital I/O (SDIO-version 3.0)
7. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
8
Jaehoon Chunge3fb6fa2014-05-16 13:59:51 +09009The Exynos DWC_mobile_storage provides four channels.
Amar070e83f2013-04-27 11:42:53 +053010SOC specific and Board specific properties are channel specific.
11
12Required SoC Specific Properties:
13
14- compatible: should be
Sam Protsenko4c6b4ae2024-08-07 22:14:21 -050015 - samsung,exynos4412-dw-mshc: for Exynos4 platforms
16 - samsung,exynos-dwmmc: for Exynos5 platforms
17 - samsung,exynos7-dw-mshc-smu: for Exynos7 platforms (with SMU block)
Amar070e83f2013-04-27 11:42:53 +053018
19- reg: physical base address of the controller and length of memory mapped
20 region.
21
22- interrupts: The interrupt number to the cpu.
23
24Required Board Specific Properties:
25
26- #address-cells: should be 1.
27- #size-cells: should be 0.
Sam Protsenko4c6b4ae2024-08-07 22:14:21 -050028- bus-width: The width of the bus used to interface the devices
Amar070e83f2013-04-27 11:42:53 +053029 supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
30 . Typically the bus width is 4 or 8.
Sam Protsenko4c6b4ae2024-08-07 22:14:21 -050031- samsung,dw-mshc-ciu-div: The divider value for the card interface unit (ciu)
32 clock (0..7).
33- samsung,dw-mshc-sdr-timing: The timing values for single data rate (SDR) mode
34 operation.
35 . First value is CIU clock phase shift value for TX mode (0..7).
36 . Second value is CIU clock phase shift value for RX mode (0..7).
37- samsung,dw-mshc-ddr-timing: The timing values for double data rate (DDR) mode
38 operation. If missing, values from samsung,dw-mshc-sdr-timing are used.
39 . First value is CIU clock phase shift value for TX mode (0..7).
40 . Second value is CIU clock phase shift value for RX mode (0..7).
Amar070e83f2013-04-27 11:42:53 +053041
42Example:
43
44mmc@12200000 {
Sam Protsenko4c6b4ae2024-08-07 22:14:21 -050045 bus-width = <8>;
46 non-removable;
47 samsung,dw-mshc-ciu-div = <3>;
48 samsung,dw-mshc-sdr-timing = <1 3>;
49 samsung,dw-mshc-ddr-timing = <0 2>;
50};
51
Amar070e83f2013-04-27 11:42:53 +053052In the above example,
53 . The bus width is 8
Sam Protsenko4c6b4ae2024-08-07 22:14:21 -050054 . Divider value for CLKSEL register is 3. The CIU clock rate will be
55 calculated as SDCLKIN / (3 + 1).
56 . SDR and DDR timings are comprised of 2 values as explained below
Amar070e83f2013-04-27 11:42:53 +053057 1 - SelClk_sample
58 3 - SelClk_drv
Sam Protsenko4c6b4ae2024-08-07 22:14:21 -050059 . The 'non-removable' flag indicates whether the particular device
Amar070e83f2013-04-27 11:42:53 +053060 cannot be removed (always present) or it is a removable device.
Sam Protsenko4c6b4ae2024-08-07 22:14:21 -050061 Flag is present - Indicates that the device cannot be removed.
62 Flag is not present - Indicates that the device is removable.