blob: 36fe34f11ecc8cf959343029207824123ad06e85 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
York Sun9941a222012-10-08 07:44:19 +00002/*
3 * Copyright 2012 Freescale Semiconductor, Inc.
York Sun9941a222012-10-08 07:44:19 +00004 */
5
York Sun9941a222012-10-08 07:44:19 +00006#include <asm/fsl_serdes.h>
7#include <asm/processor.h>
8#include <asm/io.h>
9#include "fsl_corenet2_serdes.h"
10
11struct serdes_config {
12 u32 protocol;
13 u8 lanes[SRDS_MAX_LANES];
14};
15
York Sun0fad3262016-11-21 13:35:41 -080016#ifdef CONFIG_ARCH_T4240
York Sun85e660f2013-03-25 07:33:28 +000017static const struct serdes_config serdes1_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +000018 /* SerDes 1 */
19 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
20 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
21 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
22 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
23 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
24 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
25 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
26 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
27 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
28 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
29 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
30 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
Shaohui Xied9a1d832014-05-16 10:52:33 +080031 {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
32 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
33 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
34 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +000035 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
36 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
37 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
38 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +080039 {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
40 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
41 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
42 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +000043 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
44 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
45 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
46 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +080047 {37, {NONE, NONE, QSGMII_FM1_B, NONE,
48 NONE, NONE, QSGMII_FM1_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +000049 {38, {NONE, NONE, QSGMII_FM1_B, NONE,
50 NONE, NONE, QSGMII_FM1_A, NONE}},
Shaohui Xied9a1d832014-05-16 10:52:33 +080051 {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
52 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
53 NONE, NONE, QSGMII_FM1_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +000054 {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
55 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
56 NONE, NONE, QSGMII_FM1_A, NONE}},
Shaohui Xied9a1d832014-05-16 10:52:33 +080057 {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
58 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
59 NONE, NONE, QSGMII_FM1_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +000060 {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
61 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
62 NONE, NONE, QSGMII_FM1_A, NONE}},
Shaohui Xied9a1d832014-05-16 10:52:33 +080063 {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
64 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
65 NONE, NONE, QSGMII_FM1_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +000066 {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
67 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
68 NONE, NONE, QSGMII_FM1_A, NONE}},
69 {}
70};
York Sun85e660f2013-03-25 07:33:28 +000071static const struct serdes_config serdes2_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +000072 /* SerDes 2 */
73 {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
74 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
75 XAUI_FM2_MAC10, XAUI_FM2_MAC10,
76 XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
77 {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
78 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
79 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
80 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
81 {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
82 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
83 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
84 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
Shaohui Xied9a1d832014-05-16 10:52:33 +080085 {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
86 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
87 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
88 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +000089 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
90 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
91 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
92 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +080093 {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
94 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
95 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
96 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +000097 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
98 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
99 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
100 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
101 {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
102 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
103 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
104 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800105 {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
106 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
107 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
108 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000109 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
110 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
111 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
112 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800113 {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
114 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
115 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
116 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000117 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
118 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
119 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
120 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
121 {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
122 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
123 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
124 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800125 {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
126 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
127 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
128 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000129 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
130 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
131 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
132 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
133 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
134 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
135 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
136 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800137 {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
138 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
139 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
140 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000141 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
142 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
143 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
144 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800145 {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
146 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
147 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
148 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000149 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
150 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
151 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
152 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800153 {37, {NONE, NONE, QSGMII_FM2_B, NONE,
154 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000155 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
Shaohui Xiec218d292013-08-19 18:58:52 +0800156 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800157 {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
158 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
159 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000160 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
161 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800162 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800163 {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
164 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
165 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000166 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
167 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800168 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800169 {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
170 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
171 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000172 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
173 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800174 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800175 {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
176 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
177 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000178 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
179 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800180 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800181 {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
182 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
183 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000184 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
185 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800186 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800187 {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
188 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
189 NONE, NONE, QSGMII_FM2_A, NONE} },
York Sun9941a222012-10-08 07:44:19 +0000190 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
191 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
Shaohui Xiec218d292013-08-19 18:58:52 +0800192 NONE, NONE, QSGMII_FM2_A, NONE} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800193 {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
194 XFI_FM2_MAC10, XFI_FM2_MAC9,
195 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
196 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
York Sun9941a222012-10-08 07:44:19 +0000197 {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
198 XFI_FM2_MAC10, XFI_FM2_MAC9,
199 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
200 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
201 {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
202 XFI_FM2_MAC10, XFI_FM2_MAC9,
203 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
204 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
205 {}
206};
York Sun85e660f2013-03-25 07:33:28 +0000207static const struct serdes_config serdes3_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000208 /* SerDes 3 */
Shaohui Xied9a1d832014-05-16 10:52:33 +0800209 {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
York Sun9941a222012-10-08 07:44:19 +0000210 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800211 {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
York Sun9941a222012-10-08 07:44:19 +0000212 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800213 {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
York Sun9941a222012-10-08 07:44:19 +0000214 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
Shaohui Xie0a8a3972015-07-29 11:28:36 +0800215 {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
216 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
York Sun9941a222012-10-08 07:44:19 +0000217 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
218 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
219 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
220 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800221 {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
222 PCIE2, PCIE2, PCIE2, PCIE2} },
York Sun9941a222012-10-08 07:44:19 +0000223 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
224 PCIE2, PCIE2, PCIE2, PCIE2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800225 {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
226 PCIE2, PCIE2, PCIE2, PCIE2} },
York Sun9941a222012-10-08 07:44:19 +0000227 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
228 PCIE2, PCIE2, PCIE2, PCIE2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800229 {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
230 SRIO1, SRIO1, SRIO1, SRIO1} },
York Sun9941a222012-10-08 07:44:19 +0000231 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
232 SRIO1, SRIO1, SRIO1, SRIO1}},
233 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
234 SRIO1, SRIO1, SRIO1, SRIO1}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800235 {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
236 SRIO1, SRIO1, SRIO1, SRIO1} },
York Sun9941a222012-10-08 07:44:19 +0000237 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
238 SRIO1, SRIO1, SRIO1, SRIO1}},
239 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
240 SRIO1, SRIO1, SRIO1, SRIO1}},
241 {}
242};
York Sun85e660f2013-03-25 07:33:28 +0000243static const struct serdes_config serdes4_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000244 /* SerDes 4 */
Shaohui Xied9a1d832014-05-16 10:52:33 +0800245 {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
York Sun9941a222012-10-08 07:44:19 +0000246 {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800247 {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
York Sun9941a222012-10-08 07:44:19 +0000248 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800249 {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
York Sun9941a222012-10-08 07:44:19 +0000250 {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800251 {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
York Sun9941a222012-10-08 07:44:19 +0000252 {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800253 {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
Roy Zangcc117ce2013-03-25 07:33:18 +0000254 {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800255 {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
Roy Zangcc117ce2013-03-25 07:33:18 +0000256 {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
Shaohui Xied9a1d832014-05-16 10:52:33 +0800257 {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
York Sun9941a222012-10-08 07:44:19 +0000258 {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
Shaohui Xied9a1d832014-05-16 10:52:33 +0800259 {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
York Sun9941a222012-10-08 07:44:19 +0000260 {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
261 {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
262 {}
263};
York Sunfb5137a2013-03-25 07:33:29 +0000264#else
265#error "Need to define SerDes protocol"
266#endif
York Sun85e660f2013-03-25 07:33:28 +0000267static const struct serdes_config *serdes_cfg_tbl[] = {
York Sun9941a222012-10-08 07:44:19 +0000268 serdes1_cfg_tbl,
269 serdes2_cfg_tbl,
270 serdes3_cfg_tbl,
271 serdes4_cfg_tbl,
272};
273
274enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
275{
York Sun85e660f2013-03-25 07:33:28 +0000276 const struct serdes_config *ptr;
York Sun9941a222012-10-08 07:44:19 +0000277
278 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
279 return 0;
280
281 ptr = serdes_cfg_tbl[serdes];
282 while (ptr->protocol) {
283 if (ptr->protocol == cfg)
284 return ptr->lanes[lane];
285 ptr++;
286 }
287 return 0;
288}
289
290int is_serdes_prtcl_valid(int serdes, u32 prtcl)
291{
292 int i;
York Sun85e660f2013-03-25 07:33:28 +0000293 const struct serdes_config *ptr;
York Sun9941a222012-10-08 07:44:19 +0000294
295 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
296 return 0;
297
298 ptr = serdes_cfg_tbl[serdes];
299 while (ptr->protocol) {
300 if (ptr->protocol == prtcl)
301 break;
302 ptr++;
303 }
304
305 if (!ptr->protocol)
306 return 0;
307
308 for (i = 0; i < SRDS_MAX_LANES; i++) {
309 if (ptr->lanes[i] != NONE)
310 return 1;
311 }
312
313 return 0;
314}