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git01.mediatek.com / filogic / uboot / cb5a0ffc1461cce3bc366d45938b09dff5a3d949 / . / drivers / clk / sunxi / clk_a10.c
blob: 7a96d1708ea1ede9ce2d0f180d43dd84e0a842d3 [file] [log] [blame]
Jagan Tekib38f7af2018-08-02 16:52:37 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun4i-a10-ccu.h>
13#include <dt-bindings/reset/sun4i-a10-ccu.h>
14
15static struct ccu_clk_gate a10_gates[] = {
16 [CLK_AHB_OTG] = GATE(0x060, BIT(0)),
17 [CLK_AHB_EHCI0] = GATE(0x060, BIT(1)),
18 [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)),
19 [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)),
20 [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)),
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]21 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
22 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
23 [CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
24 [CLK_AHB_MMC3] = GATE(0x060, BIT(11)),
Jagan Tekif4b29f42019-02-28 00:26:49 +0530[diff] [blame]25 [CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]26 [CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
27 [CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
28 [CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
29 [CLK_AHB_SPI3] = GATE(0x060, BIT(23)),
Jagan Tekib38f7af2018-08-02 16:52:37 +0530[diff] [blame]30
Jagan Teki53698b22019-03-28 13:46:11 +0530[diff] [blame]31 [CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
32
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]33 [CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
34 [CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
35 [CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
36 [CLK_APB1_UART3] = GATE(0x06c, BIT(19)),
37 [CLK_APB1_UART4] = GATE(0x06c, BIT(20)),
38 [CLK_APB1_UART5] = GATE(0x06c, BIT(21)),
39 [CLK_APB1_UART6] = GATE(0x06c, BIT(22)),
40 [CLK_APB1_UART7] = GATE(0x06c, BIT(23)),
41
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]42 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
43 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
44 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
45
Jagan Tekib38f7af2018-08-02 16:52:37 +0530[diff] [blame]46 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(6)),
47 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(7)),
48 [CLK_USB_PHY] = GATE(0x0cc, BIT(8)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]49
50 [CLK_SPI3] = GATE(0x0d4, BIT(31)),
Jagan Tekib38f7af2018-08-02 16:52:37 +0530[diff] [blame]51};
52
53static struct ccu_reset a10_resets[] = {
54 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
55 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
56 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
57};
58
59static const struct ccu_desc a10_ccu_desc = {
60 .gates = a10_gates,
61 .resets = a10_resets,
62};
63
64static int a10_clk_bind(struct udevice *dev)
65{
66 return sunxi_reset_bind(dev, ARRAY_SIZE(a10_resets));
67}
68
69static const struct udevice_id a10_ccu_ids[] = {
70 { .compatible = "allwinner,sun4i-a10-ccu",
71 .data = (ulong)&a10_ccu_desc },
72 { .compatible = "allwinner,sun7i-a20-ccu",
73 .data = (ulong)&a10_ccu_desc },
74 { }
75};
76
77U_BOOT_DRIVER(clk_sun4i_a10) = {
78 .name = "sun4i_a10_ccu",
79 .id = UCLASS_CLK,
80 .of_match = a10_ccu_ids,
81 .priv_auto_alloc_size = sizeof(struct ccu_priv),
82 .ops = &sunxi_clk_ops,
83 .probe = sunxi_clk_probe,
84 .bind = a10_clk_bind,
85};