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git01.mediatek.com / filogic / uboot / cb40cccecd136b8473e52ca326a9aece543dedd0 / . / arch / arm / dts / imx8mm-phycore-som.dtsi
blob: 92616bc4f71f561ba0d34e210d44e0423d4c5b86 [file] [log] [blame]
Cem Tenruhdbc57052023-07-14 10:23:26 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7#include "imx8mm.dtsi"
8#include <dt-bindings/net/ti-dp83867.h>
9
10/ {
11 model = "PHYTEC phyCORE-i.MX8MM";
12 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
13
14 aliases {
15 rtc0 = &rv3028;
16 rtc1 = &snvs_rtc;
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 reg = <0x0 0x40000000 0 0x80000000>;
22 };
23
24 reg_vdd_3v3_s: regulator-vdd-3v3-s {
25 compatible = "regulator-fixed";
26 regulator-always-on;
27 regulator-boot-on;
28 regulator-max-microvolt = <3300000>;
29 regulator-min-microvolt = <3300000>;
30 regulator-name = "VDD_3V3_S";
31 };
32};
33
34&A53_0 {
35 cpu-supply = <&reg_vdd_arm>;
36};
37
38&A53_1 {
39 cpu-supply = <&reg_vdd_arm>;
40};
41
42&A53_2 {
43 cpu-supply = <&reg_vdd_arm>;
44};
45
46&A53_3 {
47 cpu-supply = <&reg_vdd_arm>;
48};
49
50&ddrc {
51 operating-points-v2 = <&ddrc_opp_table>;
52
53 ddrc_opp_table: opp-table {
54 compatible = "operating-points-v2";
55
56 opp-25000000 {
57 opp-hz = /bits/ 64 <25000000>;
58 };
59
60 opp-100000000 {
61 opp-hz = /bits/ 64 <100000000>;
62 };
63
64 opp-750000000 {
65 opp-hz = /bits/ 64 <750000000>;
66 };
67 };
68};
69
70/* Ethernet */
71&fec1 {
72 fsl,magic-packet;
73 phy-mode = "rgmii-id";
74 phy-handle = <&ethphy0>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fec1>;
77 status = "okay";
78
79 mdio {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 ethphy0: ethernet-phy@0 {
84 compatible = "ethernet-phy-ieee802.3-c22";
85 enet-phy-lane-no-swap;
86 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
87 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
88 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
89 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
90 reg = <0>;
91 reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
92 reset-assert-us = <1000>;
93 reset-deassert-us = <1000>;
94 };
95 };
96};
97
98/* SPI Flash */
99&flexspi {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_flexspi0>;
102 status = "okay";
103
104 som_flash: flash@0 {
105 compatible = "jedec,spi-nor";
106 reg = <0>;
107 spi-max-frequency = <80000000>;
108 spi-rx-bus-width = <4>;
109 spi-tx-bus-width = <1>;
110 };
111};
112
113&gpio1 {
114 gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT",
115 "", "", "", "RESET_ETHPHY",
116 "", "", "nENABLE_FLATLINK";
117};
118
119/* I2C1 */
120&i2c1 {
121 clock-frequency = <400000>;
122 pinctrl-names = "default","gpio";
123 pinctrl-0 = <&pinctrl_i2c1>;
124 pinctrl-1 = <&pinctrl_i2c1_gpio>;
125 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
126 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
127 status = "okay";
128
129 pmic@8 {
130 compatible = "nxp,pf8121a";
131 reg = <0x08>;
132
133 regulators {
134 reg_nvcc_sd1: ldo1 {
135 regulator-always-on;
136 regulator-boot-on;
137 regulator-max-microvolt = <3300000>;
138 regulator-min-microvolt = <3300000>;
139 regulator-name = "NVCC_SD1 (LDO1)";
140
141 regulator-state-mem {
142 regulator-off-in-suspend;
143 };
144 };
145
146 reg_nvcc_sd2: ldo2 {
147 regulator-always-on;
148 regulator-boot-on;
149 regulator-max-microvolt = <3300000>;
150 regulator-min-microvolt = <1800000>;
151 regulator-name = "NVCC_SD2 (LDO2)";
152 vselect-en;
153
154 regulator-state-mem {
155 regulator-off-in-suspend;
156 };
157 };
158
159 reg_vcc_enet: ldo3 {
160 regulator-always-on;
161 regulator-boot-on;
162 regulator-max-microvolt = <2500000>;
163 regulator-min-microvolt = <1500000>;
164 regulator-name = "VCC_ENET_2V5 (LDO3)";
165
166 regulator-state-mem {
167 regulator-off-in-suspend;
168 };
169 };
170
171 reg_vdda_1v8: ldo4 {
172 regulator-always-on;
173 regulator-boot-on;
174 regulator-max-microvolt = <1800000>;
175 regulator-min-microvolt = <1500000>;
176 regulator-name = "VDDA_1V8 (LDO4)";
177
178 regulator-state-mem {
179 regulator-on-in-suspend;
180 regulator-suspend-min-microvolt = <1500000>;
181 regulator-suspend-max-microvolt = <1500000>;
182 };
183 };
184
185 reg_soc_vdda_phy: buck1 {
186 regulator-always-on;
187 regulator-boot-on;
188 regulator-max-microvolt = <900000>;
189 regulator-min-microvolt = <400000>;
190 regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)";
191
192 regulator-state-mem {
193 regulator-on-in-suspend;
194 regulator-suspend-min-microvolt = <400000>;
195 regulator-suspend-max-microvolt = <400000>;
196 };
197 };
198
199 reg_vdd_gpu_dram: buck2 {
200 regulator-always-on;
201 regulator-boot-on;
202 regulator-max-microvolt = <1000000>;
203 regulator-min-microvolt = <1000000>;
204 regulator-name = "VDD_GPU_DRAM (BUCK2)";
205
206 regulator-state-mem {
207 regulator-on-in-suspend;
208 regulator-suspend-max-microvolt = <1000000>;
209 regulator-suspend-min-microvolt = <1000000>;
210 };
211 };
212
213 reg_vdd_gpu: buck3 {
214 regulator-always-on;
215 regulator-boot-on;
216 regulator-max-microvolt = <1000000>;
217 regulator-min-microvolt = <400000>;
218 regulator-name = "VDD_VPU (BUCK3)";
219
220 regulator-state-mem {
221 regulator-off-in-suspend;
222 };
223 };
224
225 reg_vdd_mipi: buck4 {
226 regulator-always-on;
227 regulator-boot-on;
228 regulator-max-microvolt = <1050000>;
229 regulator-min-microvolt = <900000>;
230 regulator-name = "VDD_MIPI_0P9 (BUCK4)";
231
232 regulator-state-mem {
233 regulator-off-in-suspend;
234 };
235 };
236
237 reg_vdd_arm: buck5 {
238 regulator-always-on;
239 regulator-boot-on;
240 regulator-max-microvolt = <1050000>;
241 regulator-min-microvolt = <400000>;
242 regulator-name = "VDD_ARM (BUCK5)";
243
244 regulator-state-mem {
245 regulator-off-in-suspend;
246 };
247 };
248
249 reg_vdd_1v8: buck6 {
250 regulator-always-on;
251 regulator-boot-on;
252 regulator-max-microvolt = <1800000>;
253 regulator-min-microvolt = <1800000>;
254 regulator-name = "VDD_1V8 (BUCK6)";
255
256 regulator-state-mem {
257 regulator-on-in-suspend;
258 regulator-suspend-max-microvolt = <1800000>;
259 regulator-suspend-min-microvolt = <1800000>;
260 };
261 };
262
263 reg_nvcc_dram: buck7 {
264 regulator-always-on;
265 regulator-boot-on;
266 regulator-max-microvolt = <1100000>;
267 regulator-min-microvolt = <1100000>;
268 regulator-name = "NVCC_DRAM_1P1V (BUCK7)";
269 };
270
271 reg_vsnvs: vsnvs {
272 regulator-always-on;
273 regulator-boot-on;
274 regulator-max-microvolt = <1800000>;
275 regulator-min-microvolt = <1800000>;
276 regulator-name = "NVCC_SNVS_1P8 (VSNVS)";
277 };
278 };
279 };
280
281 sn65dsi83: bridge@2d {
282 compatible = "ti,sn65dsi83";
283 enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_sn65dsi83>;
286 reg = <0x2d>;
287 status = "disabled";
288 };
289
290 eeprom@51 {
291 compatible = "atmel,24c32";
292 pagesize = <32>;
293 reg = <0x51>;
294 vcc-supply = <&reg_vdd_3v3_s>;
295 };
296
297 rv3028: rtc@52 {
298 compatible = "microcrystal,rv3028";
299 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
300 interrupt-parent = <&gpio1>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_rtc>;
303 reg = <0x52>;
304 };
305};
306
307/* EMMC */
308&usdhc3 {
309 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
310 assigned-clock-rates = <400000000>;
311 bus-width = <8>;
312 keep-power-in-suspend;
313 pinctrl-names = "default", "state_100mhz", "state_200mhz";
314 pinctrl-0 = <&pinctrl_usdhc3>;
315 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
316 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
317 non-removable;
318 status = "okay";
319};
320
321/* Watchdog */
322&wdog1 {
323 fsl,ext-reset-output;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_wdog>;
326 status = "okay";
327};
328
329&iomuxc {
330 pinctrl_fec1: fec1grp {
331 fsl,pins = <
332 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2
333 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
334 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
335 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
336 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
337 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
338 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
339 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
340 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
341 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
342 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
343 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
344 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
345 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
346 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
347 >;
348 };
349
350 pinctrl_flexspi0: flexspi0grp {
351 fsl,pins = <
352 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
353 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
354 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
355 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
356 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
357 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
358 >;
359 };
360
361 pinctrl_i2c1: i2c1grp {
362 fsl,pins = <
363 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0
364 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0
365 >;
366 };
367
368 pinctrl_i2c1_gpio: i2c1gpiogrp {
369 fsl,pins = <
370 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0
371 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0
372 >;
373 };
374
375 pinctrl_rtc: rtcgrp {
376 fsl,pins = <
377 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
378 >;
379 };
380
381 pinctrl_sn65dsi83: sn65dsi83grp {
382 fsl,pins = <
383 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0
384 >;
385 };
386
387 pinctrl_usdhc3: usdhc3grp {
388 fsl,pins = <
389 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
390 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
391 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
392 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
393 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
394 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
395 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
396 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
397 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
398 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
399 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
400 >;
401 };
402
403 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
404 fsl,pins = <
405 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
406 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
407 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
408 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
409 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
410 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
411 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
412 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
413 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
414 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
415 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
416 >;
417 };
418
419 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
420 fsl,pins = <
421 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
422 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
423 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
424 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
425 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
426 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
427 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
428 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
429 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
430 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
431 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
432 >;
433 };
434
435 pinctrl_wdog: wdoggrp {
436 fsl,pins = <
437 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26
438 >;
439 };
440};