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git01.mediatek.com / filogic / uboot / cb3ed624b0616a75038c9e25f662b851ac6b4599 / . / arch / arm / dts / tegra30-asus-nexus7-grouper-PM269.dts
blob: e7765a4a6aef6e1ee0401b6fb9a81550aac1a8bf [file] [log] [blame]
Svyatoslav Ryhel88fd1562023-06-30 10:29:04 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include "tegra30-asus-grouper-common.dtsi"
5
6/ {
7 model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269";
8 compatible = "asus,grouper", "nvidia,tegra30";
9
Svyatoslav Ryhel51f70c12023-11-27 18:16:50 +0200[diff] [blame]10 pinmux@70000868 {
11 state_default: pinmux {
12 lcd_dc1_pd2 {
13 nvidia,pins = "lcd_dc1_pd2";
14 nvidia,function = "displaya";
15 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
16 nvidia,tristate = <TEGRA_PIN_DISABLE>;
17 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
18 };
19 lcd_pwr2_pc6 {
20 nvidia,pins = "lcd_pwr2_pc6";
21 nvidia,function = "displaya";
22 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
23 nvidia,tristate = <TEGRA_PIN_DISABLE>;
24 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
25 };
26 spi2_cs2_n_pw3 {
27 nvidia,pins = "spi2_cs2_n_pw3";
28 nvidia,function = "spi2";
29 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
30 nvidia,tristate = <TEGRA_PIN_DISABLE>;
31 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
32 };
33 spi1_sck_px5 {
34 nvidia,pins = "spi1_sck_px5";
35 nvidia,function = "spi1";
36 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
37 nvidia,tristate = <TEGRA_PIN_DISABLE>;
38 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
39 };
40 pu5 {
41 nvidia,pins = "pu5";
42 nvidia,function = "pwm2";
43 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
44 nvidia,tristate = <TEGRA_PIN_DISABLE>;
45 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
46 };
47 spi1_miso_px7 {
48 nvidia,pins = "spi1_miso_px7";
49 nvidia,function = "spi1";
50 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
51 nvidia,tristate = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
53 };
54 spi2_mosi_px0 {
55 nvidia,pins = "spi2_mosi_px0";
56 nvidia,function = "spi2";
57 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
58 nvidia,tristate = <TEGRA_PIN_DISABLE>;
59 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
60 };
61 kb_row7_pr7 {
62 nvidia,pins = "kb_row7_pr7";
63 nvidia,function = "kbc";
64 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
65 nvidia,tristate = <TEGRA_PIN_DISABLE>;
66 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
67 };
68 pu3 {
69 nvidia,pins = "pu3";
70 nvidia,function = "rsvd4";
71 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
72 nvidia,tristate = <TEGRA_PIN_DISABLE>;
73 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
74 };
75 pu4 {
76 nvidia,pins = "pu4";
77 nvidia,function = "pwm1";
78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <TEGRA_PIN_ENABLE>;
80 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
81 };
82 kb_row15_ps7 {
83 nvidia,pins = "kb_row15_ps7";
84 nvidia,function = "kbc";
85 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
86 nvidia,tristate = <TEGRA_PIN_DISABLE>;
87 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
88 };
89 kb_row3_pr3 {
90 nvidia,pins = "kb_row3_pr3";
91 nvidia,function = "kbc";
92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
95 };
96 kb_row13_ps5 {
97 nvidia,pins = "kb_row13_ps5";
98 nvidia,function = "kbc";
99 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
100 nvidia,tristate = <TEGRA_PIN_ENABLE>;
101 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
102 };
103 gmi_wp_n_pc7 {
104 nvidia,pins = "gmi_wp_n_pc7",
105 "gmi_wait_pi7",
106 "gmi_cs4_n_pk2",
107 "gmi_cs3_n_pk4";
108 nvidia,function = "rsvd1";
109 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
110 nvidia,tristate = <TEGRA_PIN_ENABLE>;
111 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
112 };
113 gmi_cs6_n_pi3 {
114 nvidia,pins = "gmi_cs6_n_pi3";
115 nvidia,function = "gmi";
116 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
117 nvidia,tristate = <TEGRA_PIN_ENABLE>;
118 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
119 };
120 };
121 };
122
Svyatoslav Ryhel88fd1562023-06-30 10:29:04 +0300[diff] [blame]123 i2c@7000d000 {
124 /* Texas Instruments TPS659110 PMIC */
125 pmic: tps65911@2d {
126 compatible = "ti,tps65911";
127 reg = <0x2d>;
128
129 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
132
133 ti,system-power-controller;
134
135 #gpio-cells = <2>;
136 gpio-controller;
137
138 regulators {
Svyatoslav Ryhelcaa4a462023-10-03 09:36:41 +0300[diff] [blame]139 vdd_1v8_vio: vddio {
140 regulator-name = "vdd_1v8_gen";
141 regulator-min-microvolt = <1800000>;
142 regulator-max-microvolt = <1800000>;
143 regulator-always-on;
144 regulator-boot-on;
145 };
146
Svyatoslav Ryhel88fd1562023-06-30 10:29:04 +0300[diff] [blame]147 /* eMMC VDD */
148 vcore_emmc: ldo1 {
149 regulator-name = "vdd_emmc_core";
Svyatoslav Ryhelcaa4a462023-10-03 09:36:41 +0300[diff] [blame]150 regulator-min-microvolt = <3300000>;
Svyatoslav Ryhel88fd1562023-06-30 10:29:04 +0300[diff] [blame]151 regulator-max-microvolt = <3300000>;
Svyatoslav Ryhel193e9482023-08-26 18:46:27 +0300[diff] [blame]152 regulator-boot-on;
Svyatoslav Ryhel88fd1562023-06-30 10:29:04 +0300[diff] [blame]153 };
154 };
155 };
156 };
157};