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git01.mediatek.com / filogic / uboot / cb3ed624b0616a75038c9e25f662b851ac6b4599 / . / arch / arm / dts / imx6dl-sielaff.dts
blob: 7de8d5f26518701761d03399313389e97411694e [file] [log] [blame]
Frieder Schrempf9569c932024-02-15 15:00:35 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2022 Kontron Electronics GmbH
4 */
5
6/dts-v1/;
7
8#include "imx6dl.dtsi"
9#include <dt-bindings/clock/imx6qdl-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12
13/ {
14 model = "Sielaff i.MX6 Solo";
15 compatible = "sielaff,imx6dl-board", "fsl,imx6dl";
16
17 chosen {
18 stdout-path = &uart2;
19 };
20
21 backlight: pwm-backlight {
22 compatible = "pwm-backlight";
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_backlight>;
25 pwms = <&pwm3 0 50000 0>;
26 brightness-levels = <0 0 64 88 112 136 184 232 255>;
27 default-brightness-level = <4>;
28 enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
29 power-supply = <&reg_backlight>;
30 };
31
32 cec {
33 compatible = "cec-gpio";
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_hdmi_cec>;
36 cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
37 hdmi-phandle = <&hdmi>;
38 };
39
40 enet_ref: clock-enet-ref {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <50000000>;
44 clock-output-names = "enet-ref";
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_gpio_keys>;
51
52 key-0 {
53 gpios = <&gpio2 16 0>;
54 debounce-interval = <10>;
55 linux,code = <1>;
56 };
57
58 key-1 {
59 gpios = <&gpio3 27 0>;
60 debounce-interval = <10>;
61 linux,code = <2>;
62 };
63
64 key-2 {
65 gpios = <&gpio5 4 0>;
66 debounce-interval = <10>;
67 linux,code = <3>;
68 };
69 };
70
71 leds {
72 compatible = "gpio-leds";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpio_leds>;
75
76 led-debug {
77 label = "debug-led";
78 gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
79 default-state = "off";
80 linux,default-trigger = "heartbeat";
81 };
82 };
83
84 memory@80000000 {
85 reg = <0x80000000 0x20000000>;
86 device_type = "memory";
87 };
88
89 osc_eth_phy: clock-osc-eth-phy {
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 clock-frequency = <25000000>;
93 clock-output-names = "osc-eth-phy";
94 };
95
96 panel {
97 compatible = "lg,lb070wv8";
98 backlight = <&backlight>;
99 power-supply = <&reg_3v3>;
100
101 port {
102 panel_in_lvds: endpoint {
103 remote-endpoint = <&lvds_out>;
104 };
105 };
106 };
107
108 reg_3v3: regulator-3v3 {
109 compatible = "regulator-fixed";
110 regulator-name = "3v3";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 };
114
115 reg_backlight: regulator-backlight {
116 compatible = "regulator-fixed";
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_reg_backlight>;
119 enable-active-high;
120 gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
121 regulator-name = "backlight";
122 regulator-min-microvolt = <12000000>;
123 regulator-max-microvolt = <12000000>;
124 };
125
126 reg_usb_otg_vbus: regulator-usb-otg-vbus {
127 compatible = "regulator-fixed";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
130 enable-active-high;
131 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
132 regulator-name = "usb_otg_vbus";
133 regulator-min-microvolt = <5000000>;
134 regulator-max-microvolt = <5000000>;
135 };
136};
137
138&ecspi2 {
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_ecspi2>;
141 cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
142 status = "okay";
143
144 flash@0 {
145 compatible = "jedec,spi-nor";
146 reg = <0>;
147 spi-max-frequency = <20000000>;
148 };
149};
150
151&fec {
152 /*
153 * Set PTP clock to external instead of internal reference, as the
154 * REF_CLK from the PHY is fed back into the i.MX6 and the GPR
155 * register needs to be set accordingly (see mach-imx6q.c).
156 */
157 clocks = <&clks IMX6QDL_CLK_ENET>,
158 <&clks IMX6QDL_CLK_ENET>,
159 <&enet_ref>,
160 <&clks IMX6QDL_CLK_ENET_REF>;
161 clock-names = "ipg", "ahb", "ptp", "enet_out";
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_enet>;
164 phy-connection-type = "rmii";
165 phy-handle = <&ethphy>;
166 status = "okay";
167
168 mdio {
169 #address-cells = <1>;
170 #size-cells = <0>;
171
172 ethphy: ethernet-phy@1 {
173 reg = <1>;
174 clocks = <&osc_eth_phy>;
175 clock-names = "rmii-ref";
176 micrel,led-mode = <1>;
177 reset-assert-us = <500>;
178 reset-deassert-us = <100>;
179 reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
180 };
181 };
182};
183
184&gpio1 {
185 gpio-line-names =
186 "", "", "", "", "", "", "", "",
187 "", "", "", "", "", "", "key-out", "key-in",
188 "", "", "", "", "", "", "", "",
189 "", "", "", "", "", "", "", "";
190};
191
192&gpio2 {
193 gpio-line-names =
194 "", "", "", "", "", "", "", "",
195 "lan9500a-rst", "", "", "", "", "", "", "",
196 "", "", "", "", "", "", "", "",
197 "", "", "", "", "", "", "", "";
198};
199
200&gpmi {
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_gpmi_nand>;
203 status = "okay";
204};
205
206&hdmi {
207 ddc-i2c-bus = <&i2c4>;
208 status = "okay";
209};
210
211&i2c2 {
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_i2c2>;
214 clock-frequency = <100000>;
215 status = "okay";
216
217 rtc@51 {
218 compatible = "nxp,pcf8563";
219 reg = <0x51>;
220 };
221};
222
223&i2c3 {
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_i2c3>;
226 clock-frequency = <100000>;
227 status = "okay";
228
229 touchscreen@55 {
230 compatible = "sitronix,st1633";
231 reg = <0x55>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_touch>;
234 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
235 interrupt-parent = <&gpio5>;
236 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
237 status = "disabled";
238 };
239
240 touchscreen@5d {
241 compatible = "goodix,gt928";
242 reg = <0x5d>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_touch>;
245 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
246 interrupt-parent = <&gpio5>;
247 irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
248 reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
249 status = "disabled";
250 };
251};
252
253&i2c4 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_i2c4>;
256 clock-frequency = <100000>;
257 status = "okay";
258};
259
260&ldb {
261 status = "okay";
262
263 lvds: lvds-channel@0 {
264 fsl,data-mapping = "spwg";
265 fsl,data-width = <24>;
266 status = "okay";
267
268 port@4 {
269 reg = <4>;
270
271 lvds_out: endpoint {
272 remote-endpoint = <&panel_in_lvds>;
273 };
274 };
275 };
276};
277
278&pwm3 {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_pwm3>;
281 status = "okay";
282};
283
284&uart1 {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_uart1>;
287 status = "okay";
288};
289
290&uart2 {
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_uart2>;
293 status = "okay";
294};
295
296&uart3 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_uart3>;
299 status = "okay";
300};
301
302&usbh1 {
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_usbh1>;
305 disable-over-current;
306 status = "okay";
307
308 #address-cells = <1>;
309 #size-cells = <0>;
310
311 usb1@1 {
312 compatible = "usb4b4,6570";
313 reg = <1>;
314 clocks = <&clks IMX6QDL_CLK_CKO>;
315
316 assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
317 <&clks IMX6QDL_CLK_CKO2_SEL>;
318 assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
319 <&clks IMX6QDL_CLK_OSC>;
320 assigned-clock-rates = <12000000 0>;
321 };
322};
323
324&usbotg {
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_usbotg>;
327 dr_mode = "host";
328 over-current-active-low;
329 vbus-supply = <&reg_usb_otg_vbus>;
330 status = "okay";
331};
332
333&usdhc3 {
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_usdhc3>;
336 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
337 vmmc-supply = <&reg_3v3>;
338 voltage-ranges = <3300 3300>;
339 no-1-8-v;
340 status = "okay";
341};
342
343&wdog1 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_wdog>;
346 fsl,ext-reset-output;
347 status = "okay";
348};
349
350&iomuxc {
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_hog>;
353
354 pinctrl_hog: hoggrp {
355 fsl,pins = <
356 MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */
357 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
358 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
359 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
360 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
361 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
362 >;
363 };
364
365 pinctrl_backlight: backlightgrp {
366 fsl,pins = <
367 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1
368 >;
369 };
370
371 pinctrl_ecspi2: ecspi2grp {
372 fsl,pins = <
373 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
374 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
375 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
376 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
377 >;
378 };
379
380 pinctrl_enet: enetgrp {
381 fsl,pins = <
382 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
383 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
384 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
385 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
386 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
387 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
388 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
389 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
390 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
391 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
392 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
393 >;
394 };
395
396 pinctrl_gpio_keys: gpiokeysgrp {
397 fsl,pins = <
398 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080
399 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080
400 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080
401 >;
402 };
403
404 pinctrl_gpio_leds: gpioledsgrp {
405 fsl,pins = <
406 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0
407 >;
408 };
409
410 pinctrl_gpmi_nand: gpminandgrp {
411 fsl,pins = <
412 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
413 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
414 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
415 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
416 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
417 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
418 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
419 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
420 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
421 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
422 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
423 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
424 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
425 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
426 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
427 >;
428 };
429
430 pinctrl_hdmi_cec: hdmicecgrp {
431 fsl,pins = <
432 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1
433 >;
434 };
435
436 pinctrl_i2c2: i2c2grp {
437 fsl,pins = <
438 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
439 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
440 >;
441 };
442
443 pinctrl_i2c3: i2c3grp {
444 fsl,pins = <
445 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
446 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
447 >;
448 };
449
450 pinctrl_i2c4: i2c4grp {
451 fsl,pins = <
452 MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
453 MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
454 >;
455 };
456
457 pinctrl_pwm3: pwm3grp {
458 fsl,pins = <
459 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
460 >;
461 };
462
463 pinctrl_reg_backlight: regbacklightgrp {
464 fsl,pins = <
465 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1
466 >;
467 };
468
469 pinctrl_reg_usbotg_vbus: regusbotgvbusgrp {
470 fsl,pins = <
471 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
472 >;
473 };
474
475 pinctrl_touch: touchgrp {
476 fsl,pins = <
477 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
478 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
479 >;
480 };
481
482 pinctrl_uart1: uart1grp {
483 fsl,pins = <
484 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
485 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
486 >;
487 };
488
489 pinctrl_uart2: uart2grp {
490 fsl,pins = <
491 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
492 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
493 >;
494 };
495
496 pinctrl_uart3: uart3grp {
497 fsl,pins = <
498 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
499 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
500 >;
501 };
502
503 pinctrl_usbh1: usbh1grp {
504 fsl,pins = <
505 MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1
506 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0
507 >;
508 };
509
510 pinctrl_usbotg: usbotggrp {
511 fsl,pins = <
512 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1
513 >;
514 };
515
516 pinctrl_usdhc3: usdhc3grp {
517 fsl,pins = <
518 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
519 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
520 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
521 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
522 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
523 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
524 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1
525 >;
526 };
527
528 pinctrl_wdog: wdoggrp {
529 fsl,pins = <
530 MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
531 >;
532 };
533};