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Michal Simeka4ad96e2017-11-02 10:54:48 +01001/*
2 * (C) Copyright 2013 - 2017 Xilinx.
3 *
4 * Configuration settings for the Xilinx Zynq CSE board.
5 * See zynq-common.h for Zynq common configs
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_ZYNQ_CSE_H
11#define __CONFIG_ZYNQ_CSE_H
12
13#define CONFIG_SKIP_LOWLEVEL_INIT
14#define CONFIG_SYS_DCACHE_OFF
15#define CONFIG_SYS_ICACHE_OFF
16
17#include <configs/zynq-common.h>
18
19/* Undef unneeded configs */
20#undef CONFIG_EXTRA_ENV_SETTINGS
21#undef CONFIG_BOARD_LATE_INIT
Michal Simeka4ad96e2017-11-02 10:54:48 +010022#undef CONFIG_ENV_SIZE
Michal Simeka4ad96e2017-11-02 10:54:48 +010023#undef CONFIG_ZLIB
24#undef CONFIG_GZIP
25
Michal Simeka4ad96e2017-11-02 10:54:48 +010026#undef CONFIG_SYS_CBSIZE
27#undef CONFIG_BOOTM_VXWORKS
28#undef CONFIG_BOOTM_LINUX
29
30#define CONFIG_SYS_CBSIZE 1024
31
32#define CONFIG_ENV_SIZE 400
33#undef CONFIG_SYS_INIT_RAM_ADDR
34#undef CONFIG_SYS_INIT_RAM_SIZE
35#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
36#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
37#undef CONFIG_SPL_BSS_START_ADDR
38#undef CONFIG_SPL_BSS_MAX_SIZE
39#define CONFIG_SPL_BSS_START_ADDR 0x20000
40#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
41
42#undef CONFIG_SYS_MALLOC_LEN
43#define CONFIG_SYS_MALLOC_LEN 0x1000
44
45#define CONFIG_SYS_SDRAM_BASE 0xfffc0000
46#define CONFIG_SYS_SDRAM_SIZE 0x40000
47
48#endif /* __CONFIG_ZYNQ_CSE_H */