Graeme Russ | a875dda | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 1 | /* |
2 | * (C) Copyright 2011 | ||||
3 | * Graeme Russ, <graeme.russ@gmail.com> | ||||
4 | * | ||||
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Graeme Russ | a875dda | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 6 | */ |
Bin Meng | 535109a | 2015-08-13 00:29:10 -0700 | [diff] [blame] | 7 | |
Graeme Russ | a875dda | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 8 | #include <common.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 9 | #include <linux/errno.h> |
Simon Glass | 004ba17 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 10 | #include <asm/mtrr.h> |
Graeme Russ | a875dda | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 11 | |
12 | DECLARE_GLOBAL_DATA_PTR; | ||||
13 | |||||
Simon Glass | 3297d4d | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 14 | /* Get the top of usable RAM */ |
15 | __weak ulong board_get_usable_ram_top(ulong total_size) | ||||
Graeme Russ | 3fb4f9e | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 16 | { |
Simon Glass | 3297d4d | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 17 | return gd->ram_size; |
18 | } | ||||
19 | |||||
Graeme Russ | 3fb4f9e | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 20 | int init_cache_f_r(void) |
21 | { | ||||
Simon Glass | d0594ff | 2017-01-16 07:03:46 -0700 | [diff] [blame] | 22 | #if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) |
Simon Glass | 004ba17 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 23 | int ret; |
24 | |||||
25 | ret = mtrr_commit(false); | ||||
Bin Meng | 80d2976 | 2015-01-22 11:29:41 +0800 | [diff] [blame] | 26 | /* If MTRR MSR is not implemented by the processor, just ignore it */ |
27 | if (ret && ret != -ENOSYS) | ||||
Simon Glass | 004ba17 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 28 | return ret; |
29 | #endif | ||||
Graeme Russ | 3fb4f9e | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 30 | /* Initialise the CPU cache(s) */ |
31 | return init_cache(); | ||||
32 | } |