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git01.mediatek.com / filogic / uboot / cb2accdbb2ce82afdb6e915bbee41ec5cce595ee / . / arch / arm / mach-rmobile / pfc-r8a7790.h
blob: 52f6d9e7cc1ecfe713d3471b9cb8c84f6e30ea7e [file] [log] [blame]
Nobuhiro Iwamatsuc6ccb472013-11-21 17:06:45 +0900[diff] [blame]1/*
2 * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9#ifndef __PFC_R8A7790_H__
10#define __PFC_R8A7790_H__
11
12#include <sh_pfc.h>
13#include <asm/gpio.h>
14
15#define CPU_32_PORT(fn, pfx, sfx) \
16 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
17 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
18 PORT_1(fn, pfx##31, sfx)
19
20#define CPU_32_PORT2(fn, pfx, sfx) \
21 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
22 PORT_10(fn, pfx##2, sfx)
23
24#if defined(CONFIG_R8A7790)
25#define CPU_32_PORT1(fn, pfx, sfx) \
26 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
27 PORT_10(fn, pfx##2, sfx) \
28/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
29#define CPU_ALL_PORT(fn, pfx, sfx) \
30 CPU_32_PORT(fn, pfx##_0_, sfx), \
31 CPU_32_PORT1(fn, pfx##_1_, sfx), \
32 CPU_32_PORT2(fn, pfx##_2_, sfx), \
33 CPU_32_PORT(fn, pfx##_3_, sfx), \
34 CPU_32_PORT(fn, pfx##_4_, sfx), \
35 CPU_32_PORT(fn, pfx##_5_, sfx)
36
37#elif defined(CONFIG_R8A7791)
38#define CPU_32_PORT1(fn, pfx, sfx) \
39 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
40 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
41 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
42 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
43
44/*
45 * GP_0_0_DATA -> GP_7_25_DATA
46 * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
47 * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
48 */
49#define CPU_ALL_PORT(fn, pfx, sfx) \
50 CPU_32_PORT(fn, pfx##_0_, sfx), \
51 CPU_32_PORT1(fn, pfx##_1_, sfx), \
52 CPU_32_PORT(fn, pfx##_2_, sfx), \
53 CPU_32_PORT(fn, pfx##_3_, sfx), \
54 CPU_32_PORT(fn, pfx##_4_, sfx), \
55 CPU_32_PORT(fn, pfx##_5_, sfx), \
56 CPU_32_PORT(fn, pfx##_6_, sfx), \
57 CPU_32_PORT1(fn, pfx##_7_, sfx)
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900[diff] [blame]58
59#elif defined(CONFIG_R8A7792)
60/*
61 * GP_0_0_DATA -> GP_11_29_DATA
62 * (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31]
63 * GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31])
64 */
65#define CPU_32_PORT0_28(fn, pfx, sfx) \
66 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
67 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
68 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
69 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
70 PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx), \
71 PORT_1(fn, pfx##28, sfx)
72
73#define CPU_32_PORT0_22(fn, pfx, sfx) \
74 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
75 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
76 PORT_1(fn, pfx##22, sfx)
77
78#define CPU_32_PORT0_27(fn, pfx, sfx) \
79 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
80 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
81 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
82 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
83 PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
84
85#define CPU_32_PORT0_16(fn, pfx, sfx) \
86 PORT_10(fn, pfx, sfx), \
87 PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \
88 PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \
89 PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \
90 PORT_1(fn, pfx##16, sfx)
91
92#define CPU_ALL_PORT(fn, pfx, sfx) \
93 CPU_32_PORT0_28(fn, pfx##_0_, sfx), \
94 CPU_32_PORT0_22(fn, pfx##_1_, sfx), \
95 CPU_32_PORT(fn, pfx##_2_, sfx), \
96 CPU_32_PORT0_27(fn, pfx##_3_, sfx), \
97 CPU_32_PORT0_16(fn, pfx##_4_, sfx), \
98 CPU_32_PORT0_16(fn, pfx##_5_, sfx), \
99 CPU_32_PORT0_16(fn, pfx##_6_, sfx), \
100 CPU_32_PORT0_16(fn, pfx##_7_, sfx), \
101 CPU_32_PORT0_16(fn, pfx##_8_, sfx), \
102 CPU_32_PORT0_16(fn, pfx##_9_, sfx), \
103 CPU_32_PORT(fn, pfx##_10_, sfx), \
104 CPU_32_PORT2(fn, pfx##_11_, sfx)
105
Nobuhiro Iwamatsuc6ccb472013-11-21 17:06:45 +0900[diff] [blame]106#else
107#error "NO support"
108#endif
109
110#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
111#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
112 GP##pfx##_IN, GP##pfx##_OUT)
113
114#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
115#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
116
117#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
118#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
119#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
120
121#define PORT_10_REV(fn, pfx, sfx) \
122 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
123 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
124 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
125 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
126 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
127
128#define CPU_32_PORT_REV(fn, pfx, sfx) \
129 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
130 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
131 PORT_10_REV(fn, pfx, sfx)
132
133#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
134#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
135
136#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
137#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
138 FN_##ipsr, FN_##fn)
139
140#endif /* __PFC_R8A7790_H__ */