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Marek Vasutc140e982011-11-08 23:18:08 +00001/*
Otavio Salvador5309b002012-08-05 09:05:30 +00002 * Freescale i.MXS Register Accessors
Marek Vasutc140e982011-11-08 23:18:08 +00003 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Marek Vasutc140e982011-11-08 23:18:08 +00008 */
9
Otavio Salvador5309b002012-08-05 09:05:30 +000010#ifndef __MXS_REGS_COMMON_H__
11#define __MXS_REGS_COMMON_H__
Marek Vasutc140e982011-11-08 23:18:08 +000012
Peng Fan2728f832015-10-29 15:54:42 +080013#include <linux/types.h>
14
Marek Vasutc140e982011-11-08 23:18:08 +000015/*
Otavio Salvador5309b002012-08-05 09:05:30 +000016 * The i.MXS has interesting feature when it comes to register access. There
Marek Vasutc140e982011-11-08 23:18:08 +000017 * are four kinds of access to one particular register. Those are:
18 *
19 * 1) Common read/write access. To use this mode, just write to the address of
20 * the register.
21 * 2) Set bits only access. To set bits, write which bits you want to set to the
22 * address of the register + 0x4.
23 * 3) Clear bits only access. To clear bits, write which bits you want to clear
24 * to the address of the register + 0x8.
25 * 4) Toggle bits only access. To toggle bits, write which bits you want to
26 * toggle to the address of the register + 0xc.
27 *
28 * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
29 * can be set/cleared by pure write as in access type 1, some need to be
30 * explicitly set/cleared by using access type 2-3.
31 *
32 * The following macros and structures allow the user to either access the
33 * register in all aforementioned modes (by accessing reg_name, reg_name_set,
34 * reg_name_clr, reg_name_tog) or pass the register structure further into
35 * various functions with correct type information (by accessing reg_name_reg).
36 *
37 */
38
Otavio Salvador5309b002012-08-05 09:05:30 +000039#define __mxs_reg_8(name) \
Robert Deliene4d40fe2012-02-26 12:15:06 +000040 uint8_t name[4]; \
41 uint8_t name##_set[4]; \
42 uint8_t name##_clr[4]; \
43 uint8_t name##_tog[4]; \
44
Otavio Salvador5309b002012-08-05 09:05:30 +000045#define __mxs_reg_32(name) \
Marek Vasutc140e982011-11-08 23:18:08 +000046 uint32_t name; \
47 uint32_t name##_set; \
48 uint32_t name##_clr; \
49 uint32_t name##_tog;
50
Otavio Salvador5309b002012-08-05 09:05:30 +000051struct mxs_register_8 {
52 __mxs_reg_8(reg)
Robert Deliene4d40fe2012-02-26 12:15:06 +000053};
54
Otavio Salvador5309b002012-08-05 09:05:30 +000055struct mxs_register_32 {
56 __mxs_reg_32(reg)
Marek Vasutc140e982011-11-08 23:18:08 +000057};
58
Otavio Salvador5309b002012-08-05 09:05:30 +000059#define mxs_reg_8(name) \
Robert Deliene4d40fe2012-02-26 12:15:06 +000060 union { \
Otavio Salvador5309b002012-08-05 09:05:30 +000061 struct { __mxs_reg_8(name) }; \
62 struct mxs_register_8 name##_reg; \
Robert Deliene4d40fe2012-02-26 12:15:06 +000063 };
64
Otavio Salvador5309b002012-08-05 09:05:30 +000065#define mxs_reg_32(name) \
Marek Vasutc140e982011-11-08 23:18:08 +000066 union { \
Otavio Salvador5309b002012-08-05 09:05:30 +000067 struct { __mxs_reg_32(name) }; \
68 struct mxs_register_32 name##_reg; \
Marek Vasutc140e982011-11-08 23:18:08 +000069 };
70
Otavio Salvador5309b002012-08-05 09:05:30 +000071#endif /* __MXS_REGS_COMMON_H__ */