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git01.mediatek.com / filogic / uboot / cb2accdbb2ce82afdb6e915bbee41ec5cce595ee / . / arch / arm / include / asm / arch-lpc32xx / config.h
blob: 988a8518329d1387132ef5f15cbeb75758d4ce07 [file] [log] [blame]
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]1/*
2 * Common definitions for LPC32XX board configurations
3 *
Vladimir Zapolskiydb6a14f2015-02-12 00:24:20 +0200[diff] [blame]4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]7 */
8
9#ifndef _LPC32XX_CONFIG_H
10#define _LPC32XX_CONFIG_H
11
Vladimir Zapolskiydb6a14f2015-02-12 00:24:20 +0200[diff] [blame]12
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]13/* Basic CPU architecture */
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]14#define CONFIG_ARCH_CPU_INIT
15
16#define CONFIG_NR_DRAM_BANKS_MAX 2
17
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]18/* UART configuration */
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]19#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]20 (CONFIG_SYS_LPC32XX_UART == 7)
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]21#if !defined(CONFIG_LPC32XX_HSUART)
22#define CONFIG_LPC32XX_HSUART
23#endif
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]24#endif
25
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]26#if !defined(CONFIG_SYS_NS16550_CLK)
27#define CONFIG_SYS_NS16550_CLK 13000000
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]28#endif
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]29
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]30#define CONFIG_SYS_BAUDRATE_TABLE \
31 { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
32
Albert ARIBAUD \(3ADEV\)391e1632015-03-31 11:40:43 +0200[diff] [blame]33/* Ethernet */
34#define LPC32XX_ETH_BASE ETHERNET_BASE
35
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]36/* NAND */
37#if defined(CONFIG_NAND_LPC32XX_SLC)
38#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800
39#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
40
41#if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
42#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
43#endif
44
45#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
46#define CONFIG_SYS_NAND_OOBSIZE 64
47#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48 48, 49, 50, 51, 52, 53, 54, 55, \
49 56, 57, 58, 59, 60, 61, 62, 63, }
50#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
51#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
52#define CONFIG_SYS_NAND_OOBSIZE 16
53#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
54#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
55#else
56#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
57#endif
58
59#define CONFIG_SYS_NAND_ECCSIZE 0x100
60#define CONFIG_SYS_NAND_ECCBYTES 3
61#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
62 CONFIG_SYS_NAND_PAGE_SIZE)
63#endif /* CONFIG_NAND_LPC32XX_SLC */
64
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]65/* NOR Flash */
66#if defined(CONFIG_SYS_FLASH_CFI)
67#define CONFIG_FLASH_CFI_DRIVER
68#define CONFIG_SYS_FLASH_PROTECTION
69#endif
70
Vladimir Zapolskiy69ec0752015-08-12 20:32:08 +0300[diff] [blame]71/* USB OHCI */
72#if defined(CONFIG_USB_OHCI_LPC32XX)
73#define CONFIG_USB_OHCI_NEW
74#define CONFIG_SYS_USB_OHCI_CPU_INIT
75#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
76#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
77#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci"
78#endif
79
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]80#endif /* _LPC32XX_CONFIG_H */