blob: 1aa29e541ec5bb73a8db02c97ca805e34a23be11 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wang Huanddf89f92014-09-05 13:52:45 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Hou Zhiqiangce6e3912022-04-22 13:50:06 +05304 * Copyright 2019, 2021 NXP
Wang Huanddf89f92014-09-05 13:52:45 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Wang Huanddf89f92014-09-05 13:52:45 +080010#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
11#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
12
York Sun1006cad2015-04-29 10:35:35 -070013#define DDR_SDRAM_CFG 0x470c0008
14#define DDR_CS0_BNDS 0x008000bf
15#define DDR_CS0_CONFIG 0x80014302
16#define DDR_TIMING_CFG_0 0x50550004
17#define DDR_TIMING_CFG_1 0xbcb38c56
18#define DDR_TIMING_CFG_2 0x0040d120
19#define DDR_TIMING_CFG_3 0x010e1000
20#define DDR_TIMING_CFG_4 0x00000001
21#define DDR_TIMING_CFG_5 0x03401400
22#define DDR_SDRAM_CFG_2 0x00401010
23#define DDR_SDRAM_MODE 0x00061c60
24#define DDR_SDRAM_MODE_2 0x00180000
25#define DDR_SDRAM_INTERVAL 0x18600618
26#define DDR_DDR_WRLVL_CNTL 0x8655f605
27#define DDR_DDR_WRLVL_CNTL_2 0x05060607
28#define DDR_DDR_WRLVL_CNTL_3 0x05050505
29#define DDR_DDR_CDR1 0x80040000
30#define DDR_DDR_CDR2 0x00000001
31#define DDR_SDRAM_CLK_CNTL 0x02000000
32#define DDR_DDR_ZQ_CNTL 0x89080600
33#define DDR_CS0_CONFIG_2 0
34#define DDR_SDRAM_CFG_MEM_EN 0x80000000
Tang Yuantian8b160bc2015-05-14 17:20:28 +080035#define SDRAM_CFG2_D_INIT 0x00000010
36#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
37#define SDRAM_CFG2_FRC_SR 0x80000000
38#define SDRAM_CFG_BI 0x00000001
York Sun1006cad2015-04-29 10:35:35 -070039
Alison Wang948c6092014-12-03 15:00:48 +080040#ifdef CONFIG_SD_BOOT
Udit Agarwal22ec2382019-11-07 16:11:32 +000041#ifdef CONFIG_NXP_ESBC
Sumit Garge2ca9432016-06-14 13:52:40 -040042/*
43 * HDR would be appended at end of image and copied to DDR along
44 * with U-Boot image.
45 */
Semen Protsenkod776ecf2016-11-16 19:19:06 +020046#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
Udit Agarwal22ec2382019-11-07 16:11:32 +000047#endif /* ifdef CONFIG_NXP_ESBC */
Alison Wang948c6092014-12-03 15:00:48 +080048
Sumit Garge2ca9432016-06-14 13:52:40 -040049#ifdef CONFIG_U_BOOT_HDR_SIZE
50/*
51 * HDR would be appended at end of image and copied to DDR along
52 * with U-Boot image. Here u-boot max. size is 512K. So if binary
53 * size increases then increase this size in case of secure boot as
54 * it uses raw u-boot image instead of fit image.
55 */
Vinitha Pillai31b11c62017-02-01 18:28:53 +053056#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
Sumit Garge2ca9432016-06-14 13:52:40 -040057#else
Vinitha Pillai31b11c62017-02-01 18:28:53 +053058#define CONFIG_SYS_MONITOR_LEN 0x100000
Sumit Garge2ca9432016-06-14 13:52:40 -040059#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
Alison Wang948c6092014-12-03 15:00:48 +080060#endif
61
Wang Huanddf89f92014-09-05 13:52:45 +080062#define PHYS_SDRAM 0x80000000
63#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
64
65#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
66#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
67
Wang Huanddf89f92014-09-05 13:52:45 +080068/*
69 * IFC Definitions
70 */
Alison Wangdd45cc52015-10-15 17:54:40 +080071#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanddf89f92014-09-05 13:52:45 +080072#define CONFIG_SYS_FLASH_BASE 0x60000000
73#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
74
75#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
76#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
77 CSPR_PORT_SIZE_16 | \
78 CSPR_MSEL_NOR | \
79 CSPR_V)
80#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
81
82/* NOR Flash Timing Params */
83#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
84 CSOR_NOR_TRHZ_80)
85#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
86 FTIM0_NOR_TEADC(0x5) | \
87 FTIM0_NOR_TAVDS(0x0) | \
88 FTIM0_NOR_TEAHC(0x5))
89#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
90 FTIM1_NOR_TRAD_NOR(0x1A) | \
91 FTIM1_NOR_TSEQRAD_NOR(0x13))
92#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
93 FTIM2_NOR_TCH(0x4) | \
94 FTIM2_NOR_TWP(0x1c) | \
95 FTIM2_NOR_TWPH(0x0e))
96#define CONFIG_SYS_NOR_FTIM3 0
97
Wang Huanddf89f92014-09-05 13:52:45 +080098#define CONFIG_SYS_FLASH_QUIET_TEST
99#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
100
Wang Huanddf89f92014-09-05 13:52:45 +0800101#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
102#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
103#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
104
105#define CONFIG_SYS_FLASH_EMPTY_INFO
106#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
107
Yuan Yaoda17d1a2014-10-17 15:26:34 +0800108#define CONFIG_SYS_WRITE_SWAPPED_DATA
Alison Wang2145a372014-12-09 17:38:02 +0800109#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800110
111/* CPLD */
112
113#define CONFIG_SYS_CPLD_BASE 0x7fb00000
114#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
115
116#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
117#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
118 CSPR_PORT_SIZE_8 | \
119 CSPR_MSEL_GPCM | \
120 CSPR_V)
121#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
122#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
123 CSOR_NOR_NOR_MODE_AVD_NOR | \
124 CSOR_NOR_TRHZ_80)
125
126/* CPLD Timing parameters for IFC GPCM */
127#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
128 FTIM0_GPCM_TEADC(0xf) | \
129 FTIM0_GPCM_TEAHC(0xf))
130#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
131 FTIM1_GPCM_TRAD(0x3f))
132#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
133 FTIM2_GPCM_TCH(0xf) | \
134 FTIM2_GPCM_TWP(0xff))
135#define CONFIG_SYS_FPGA_FTIM3 0x0
136#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
137#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
138#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
139#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
140#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
141#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
142#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
143#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
144#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
145#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
146#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
147#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
148#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
149#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
150#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
151#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
152
153/*
154 * Serial Port
155 */
Tom Rini037415a2022-03-23 17:20:00 -0400156#ifndef CONFIG_LPUART
Wang Huanddf89f92014-09-05 13:52:45 +0800157#define CONFIG_SYS_NS16550_SERIAL
Bin Meng06229a92016-01-13 19:38:59 -0800158#ifndef CONFIG_DM_SERIAL
Wang Huanddf89f92014-09-05 13:52:45 +0800159#define CONFIG_SYS_NS16550_REG_SIZE 1
Bin Meng06229a92016-01-13 19:38:59 -0800160#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800161#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wang2a397ce2015-01-04 15:30:59 +0800162#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800163
Wang Huanddf89f92014-09-05 13:52:45 +0800164/*
165 * I2C
166 */
Wang Huanddf89f92014-09-05 13:52:45 +0800167
Biwen Lie5bd7132021-02-05 19:02:02 +0800168/* GPIO */
Biwen Lie5bd7132021-02-05 19:02:02 +0800169
Alison Wangaf276f42014-10-17 15:26:35 +0800170/* EEPROM */
Alison Wangaf276f42014-10-17 15:26:35 +0800171#define CONFIG_SYS_I2C_EEPROM_NXID
172#define CONFIG_SYS_EEPROM_BUS_NUM 1
Alison Wangaf276f42014-10-17 15:26:35 +0800173
Xiubo Li563e3ce2014-11-21 17:40:57 +0800174#define CONFIG_PEN_ADDR_BIG_ENDIAN
175#define CONFIG_SMP_PEN_ADDR 0x01ee0200
Xiubo Li563e3ce2014-11-21 17:40:57 +0800176
Wang Huanddf89f92014-09-05 13:52:45 +0800177#define CONFIG_HWCONFIG
Zhuoyu Zhangfe4f2882015-08-17 18:55:12 +0800178#define HWCONFIG_BUFFER_SIZE 256
179
180#define CONFIG_FSL_DEVICE_DISABLE
Wang Huanddf89f92014-09-05 13:52:45 +0800181
Alison Wanga999c9d2017-05-26 15:46:15 +0800182#define BOOT_TARGET_DEVICES(func) \
183 func(MMC, mmc, 0) \
Yunfeng Ding0c1d95e2019-02-19 14:44:04 +0800184 func(USB, usb, 0) \
185 func(DHCP, dhcp, na)
Alison Wanga999c9d2017-05-26 15:46:15 +0800186#include <config_distro_bootcmd.h>
Wang Huanddf89f92014-09-05 13:52:45 +0800187
Alison Wang2a397ce2015-01-04 15:30:59 +0800188#ifdef CONFIG_LPUART
189#define CONFIG_EXTRA_ENV_SETTINGS \
Alison Wang6a8e9782020-04-23 22:37:34 +0800190 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
191 "cma=64M@0x0-0xb0000000\0" \
Alison Wangec2ab3c2015-10-26 14:08:28 +0800192 "initrd_high=0xffffffff\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800193 "kernel_addr=0x65000000\0" \
194 "scriptaddr=0x80000000\0" \
Sumit Garg50f14672017-06-06 20:51:31 +0530195 "scripthdraddr=0x80080000\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800196 "fdtheader_addr_r=0x80100000\0" \
197 "kernelheader_addr_r=0x80200000\0" \
198 "kernel_addr_r=0x81000000\0" \
199 "fdt_addr_r=0x90000000\0" \
200 "ramdisk_addr_r=0xa0000000\0" \
201 "load_addr=0xa0000000\0" \
202 "kernel_size=0x2800000\0" \
Shengzhou Liu7c8dbe22017-11-09 17:57:57 +0800203 "kernel_addr_sd=0x8000\0" \
204 "kernel_size_sd=0x14000\0" \
Alison Wangd168ade2020-01-21 07:33:01 +0000205 "othbootargs=cma=64M@0x0-0xb0000000\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800206 BOOTENV \
207 "boot_scripts=ls1021atwr_boot.scr\0" \
Sumit Garg50f14672017-06-06 20:51:31 +0530208 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800209 "scan_dev_for_boot_part=" \
210 "part list ${devtype} ${devnum} devplist; " \
211 "env exists devplist || setenv devplist 1; " \
212 "for distro_bootpart in ${devplist}; do " \
213 "if fstype ${devtype} " \
214 "${devnum}:${distro_bootpart} " \
215 "bootfstype; then " \
216 "run scan_dev_for_boot; " \
217 "fi; " \
218 "done\0" \
Sumit Garg50f14672017-06-06 20:51:31 +0530219 "scan_dev_for_boot=" \
220 "echo Scanning ${devtype} " \
221 "${devnum}:${distro_bootpart}...; " \
222 "for prefix in ${boot_prefixes}; do " \
223 "run scan_dev_for_scripts; " \
224 "done;" \
225 "\0" \
226 "boot_a_script=" \
227 "load ${devtype} ${devnum}:${distro_bootpart} " \
228 "${scriptaddr} ${prefix}${script}; " \
229 "env exists secureboot && load ${devtype} " \
230 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai25355ec2019-04-23 05:52:17 +0000231 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
232 "env exists secureboot " \
Sumit Garg50f14672017-06-06 20:51:31 +0530233 "&& esbc_validate ${scripthdraddr};" \
234 "source ${scriptaddr}\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800235 "installer=load mmc 0:2 $load_addr " \
236 "/flex_installer_arm32.itb; " \
237 "bootm $load_addr#ls1021atwr\0" \
238 "qspi_bootcmd=echo Trying load from qspi..;" \
239 "sf probe && sf read $load_addr " \
240 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
241 "nor_bootcmd=echo Trying load from nor..;" \
242 "cp.b $kernel_addr $load_addr " \
243 "$kernel_size && bootm $load_addr#$board\0"
Alison Wang2a397ce2015-01-04 15:30:59 +0800244#else
Wang Huanddf89f92014-09-05 13:52:45 +0800245#define CONFIG_EXTRA_ENV_SETTINGS \
Alison Wang6a8e9782020-04-23 22:37:34 +0800246 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
247 "cma=64M@0x0-0xb0000000\0" \
Alison Wangec2ab3c2015-10-26 14:08:28 +0800248 "initrd_high=0xffffffff\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530249 "kernel_addr=0x61000000\0" \
250 "kernelheader_addr=0x60800000\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800251 "scriptaddr=0x80000000\0" \
Sumit Garg50f14672017-06-06 20:51:31 +0530252 "scripthdraddr=0x80080000\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800253 "fdtheader_addr_r=0x80100000\0" \
254 "kernelheader_addr_r=0x80200000\0" \
255 "kernel_addr_r=0x81000000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530256 "kernelheader_size=0x40000\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800257 "fdt_addr_r=0x90000000\0" \
258 "ramdisk_addr_r=0xa0000000\0" \
259 "load_addr=0xa0000000\0" \
260 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530261 "kernel_addr_sd=0x8000\0" \
262 "kernel_size_sd=0x14000\0" \
263 "kernelhdr_addr_sd=0x4000\0" \
264 "kernelhdr_size_sd=0x10\0" \
Alison Wangd168ade2020-01-21 07:33:01 +0000265 "othbootargs=cma=64M@0x0-0xb0000000\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800266 BOOTENV \
267 "boot_scripts=ls1021atwr_boot.scr\0" \
Sumit Garg50f14672017-06-06 20:51:31 +0530268 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800269 "scan_dev_for_boot_part=" \
270 "part list ${devtype} ${devnum} devplist; " \
271 "env exists devplist || setenv devplist 1; " \
272 "for distro_bootpart in ${devplist}; do " \
273 "if fstype ${devtype} " \
274 "${devnum}:${distro_bootpart} " \
275 "bootfstype; then " \
276 "run scan_dev_for_boot; " \
277 "fi; " \
278 "done\0" \
Sumit Garg50f14672017-06-06 20:51:31 +0530279 "scan_dev_for_boot=" \
280 "echo Scanning ${devtype} " \
281 "${devnum}:${distro_bootpart}...; " \
282 "for prefix in ${boot_prefixes}; do " \
283 "run scan_dev_for_scripts; " \
284 "done;" \
285 "\0" \
286 "boot_a_script=" \
287 "load ${devtype} ${devnum}:${distro_bootpart} " \
288 "${scriptaddr} ${prefix}${script}; " \
289 "env exists secureboot && load ${devtype} " \
290 "${devnum}:${distro_bootpart} " \
291 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
292 "&& esbc_validate ${scripthdraddr};" \
293 "source ${scriptaddr}\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800294 "qspi_bootcmd=echo Trying load from qspi..;" \
295 "sf probe && sf read $load_addr " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530296 "$kernel_addr $kernel_size; env exists secureboot " \
297 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
298 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
299 "bootm $load_addr#$board\0" \
Alison Wanga999c9d2017-05-26 15:46:15 +0800300 "nor_bootcmd=echo Trying load from nor..;" \
301 "cp.b $kernel_addr $load_addr " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530302 "$kernel_size; env exists secureboot " \
303 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
304 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
305 "bootm $load_addr#$board\0" \
Shengzhou Liu7c8dbe22017-11-09 17:57:57 +0800306 "sd_bootcmd=echo Trying load from SD ..;" \
307 "mmcinfo && mmc read $load_addr " \
308 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530309 "env exists secureboot && mmc read $kernelheader_addr_r " \
310 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
311 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu7c8dbe22017-11-09 17:57:57 +0800312 "bootm $load_addr#$board\0"
Alison Wang2a397ce2015-01-04 15:30:59 +0800313#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800314
315/*
316 * Miscellaneous configurable options
317 */
Alison Wang71477062020-02-03 15:25:19 +0800318#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Wang Huanddf89f92014-09-05 13:52:45 +0800319
Xiubo Li03d40aa2014-11-21 17:40:59 +0800320#define CONFIG_LS102XA_STREAM_ID
321
Wang Huanddf89f92014-09-05 13:52:45 +0800322/*
323 * Environment
324 */
Wang Huanddf89f92014-09-05 13:52:45 +0800325
Aneesh Bansal962021a2016-01-22 16:37:22 +0530326#include <asm/fsl_secure_boot.h>
Ruchika Gupta901ae762014-10-15 11:39:06 +0530327
Wang Huanddf89f92014-09-05 13:52:45 +0800328#endif