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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +01002/*
3 * Imagination Technologies MIPSfpga platform code
4 *
5 * Copyright (C) 2016, Imagination Technologies Ltd.
6 *
7 * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
8 *
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +01009 */
10
11#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -060012#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010014
Simon Glass39f90ba2017-03-31 08:40:25 -060015DECLARE_GLOBAL_DATA_PTR;
16
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010017/* initialize the DDR Controller and PHY */
Simon Glassd35f3382017-04-06 12:47:05 -060018int dram_init(void)
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010019{
20 /* MIG IP block is smart and doesn't need SW
21 * to do any init */
Tom Rinibb4dd962022-11-16 13:10:37 -050022 gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */
Simon Glass39f90ba2017-03-31 08:40:25 -060023
24 return 0;
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010025}