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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada133b1262017-01-21 18:05:31 +09002/*
Masahiro Yamada616933d92017-08-26 17:58:00 +09003 * Copyright (C) 2017 Socionext Inc.
Masahiro Yamada133b1262017-01-21 18:05:31 +09004 */
5
Masahiro Yamada616933d92017-08-26 17:58:00 +09006#include <linux/delay.h>
7
Masahiro Yamada5e05c4d2017-06-22 16:42:04 +09008#include "../init.h"
Masahiro Yamada616933d92017-08-26 17:58:00 +09009#include "../sc64-regs.h"
10#include "pll.h"
11
12/* PLL type: SSC */
Masahiro Yamadac84024c2019-07-10 20:07:41 +090013#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
14#define SC_SPLLCTRL 0x1410 /* misc */
15#define SC_SPLL2CTRL 0x1420 /* DSP */
16#define SC_VPPLLCTRL 0x1430 /* VPE */
17#define SC_VGPLLCTRL 0x1440
18#define SC_DECPLLCTRL 0x1450
19#define SC_ENCPLLCTRL 0x1460
20#define SC_PXFPLLCTRL 0x1470
21#define SC_DPLL0CTRL 0x1480 /* DDR memory 0 */
22#define SC_DPLL1CTRL 0x1490 /* DDR memory 1 */
23#define SC_DPLL2CTRL 0x14a0 /* DDR memory 2 */
24#define SC_VSPLLCTRL 0x14c0
Masahiro Yamada616933d92017-08-26 17:58:00 +090025
26/* PLL type: VPLL27 */
Masahiro Yamadac84024c2019-07-10 20:07:41 +090027#define SC_VPLL27FCTRL 0x1500
28#define SC_VPLL27ACTRL 0x1520
Masahiro Yamada616933d92017-08-26 17:58:00 +090029
30/* PLL type: DSPLL */
Masahiro Yamadac84024c2019-07-10 20:07:41 +090031#define SC_VPLL8KCTRL 0x1540
Masahiro Yamada5e05c4d2017-06-22 16:42:04 +090032
Masahiro Yamada133b1262017-01-21 18:05:31 +090033void uniphier_pxs3_pll_init(void)
34{
Masahiro Yamada616933d92017-08-26 17:58:00 +090035 uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
36 /* do nothing for SPLL */
37 uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
38 uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
39 uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
40 uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
41 uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
42 uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
43 uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
44
45 mdelay(1);
46
47 uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
48 uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
49 uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
50 uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL);
51 uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL);
52 uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL);
53 uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL);
54 uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
55 uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
56 uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
57 uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
58
59 uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
60 uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
61
62 uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
Masahiro Yamada133b1262017-01-21 18:05:31 +090063}