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git01.mediatek.com / filogic / uboot / cb0da87fc4aeac8c98f34ae7779730a801b0f493 / . / include / configs / XPEDITE5370.h
blob: 26b798b4d8a56eb32e17c18049c72a93c6141bca [file] [log] [blame]
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]1/*
2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * xpedite5370 board configuration file
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36#define CONFIG_MPC8572 1
37#define CONFIG_XPEDITE5370 1
38#define CONFIG_SYS_BOARD_NAME "XPedite5370"
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]39#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]40
41#define CONFIG_PCI 1 /* Enable PCI/PCIE */
42#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
43#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
44#define CONFIG_PCIE1 1 /* PCIE controler 1 */
45#define CONFIG_PCIE2 1 /* PCIE controler 2 */
46#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
47#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
48#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
49#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
50
51/*
52 * DDR config
53 */
54#define CONFIG_FSL_DDR2
55#undef CONFIG_FSL_DDR_INTERACTIVE
56#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
57#define CONFIG_DDR_SPD
58#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
59#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
60#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
61#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
62#define CONFIG_NUM_DDR_CONTROLLERS 2
63#define CONFIG_DIMM_SLOTS_PER_CTLR 1
64#define CONFIG_CHIP_SELECTS_PER_CTRL 1
65#define CONFIG_DDR_ECC
66#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
67#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
68#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
69#define CONFIG_VERY_BIG_RAM
70
71#ifndef __ASSEMBLY__
72extern unsigned long get_board_sys_clk(unsigned long dummy);
73extern unsigned long get_board_ddr_clk(unsigned long dummy);
74#endif
75
76#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
77#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
78
79/*
80 * These can be toggled for performance analysis, otherwise use default.
81 */
82#define CONFIG_L2_CACHE /* toggle L2 cache */
83#define CONFIG_BTB /* toggle branch predition */
84#define CONFIG_ENABLE_36BIT_PHYS 1
85
86/*
87 * Base addresses -- Note these are effective addresses where the
88 * actual resources get mapped (not physical addresses)
89 */
90#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
91#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
92#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
93#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
94#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
95#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
96
97/*
98 * Diagnostics
99 */
100#define CONFIG_SYS_ALT_MEMTEST
101#define CONFIG_SYS_MEMTEST_START 0x10000000
102#define CONFIG_SYS_MEMTEST_END 0x20000000
103
104/*
105 * Memory map
106 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
107 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
108 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
109 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
110 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
111 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
112 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
113 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
114 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
115 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
116 */
117
Kumar Gala6fa11c12009-09-15 22:21:58 -0500[diff] [blame]118#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]119
120/*
121 * NAND flash configuration
122 */
123#define CONFIG_SYS_NAND_BASE 0xef800000
124#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
Peter Tyser95947f92009-07-21 13:51:08 -0500[diff] [blame]125#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
126 CONFIG_SYS_NAND_BASE2}
127#define CONFIG_SYS_MAX_NAND_DEVICE 2
128#define CONFIG_MTD_NAND_VERIFY_WRITE
129#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
130#define CONFIG_NAND_FSL_ELBC
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]131
132/*
133 * NOR flash configuration
134 */
135#define CONFIG_SYS_FLASH_BASE 0xf8000000
136#define CONFIG_SYS_FLASH_BASE2 0xf0000000
137#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
138#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
139#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
140#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
141#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
142#define CONFIG_FLASH_CFI_DRIVER
143#define CONFIG_SYS_FLASH_CFI
Peter Tyser977b0b72009-07-19 19:17:40 -0500[diff] [blame]144#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]145#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
146 {0xf7f40000, 0xc0000} }
147#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
148
149/*
150 * Chip select configuration
151 */
152/* NOR Flash 0 on CS0 */
153#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
154 BR_PS_16 | \
155 BR_V)
156#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
157 OR_GPCM_CSNT | \
158 OR_GPCM_XACS | \
159 OR_GPCM_ACS_DIV2 | \
160 OR_GPCM_SCY_8 | \
161 OR_GPCM_TRLX | \
162 OR_GPCM_EHTR | \
163 OR_GPCM_EAD)
164
165/* NOR Flash 1 on CS1 */
166#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
167 BR_PS_16 | \
168 BR_V)
169#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
170
171/* NAND flash on CS2 */
172#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
173 (2<<BR_DECC_SHIFT) | \
174 BR_PS_8 | \
175 BR_MS_FCM | \
176 BR_V)
177
178/* NAND flash on CS2 */
179#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
180 OR_FCM_PGS | \
181 OR_FCM_CSCT | \
182 OR_FCM_CST | \
183 OR_FCM_CHT | \
184 OR_FCM_SCY_1 | \
185 OR_FCM_TRLX | \
186 OR_FCM_EHTR)
187
188/* NAND flash on CS3 */
189#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
190 (2<<BR_DECC_SHIFT) | \
191 BR_PS_8 | \
192 BR_MS_FCM | \
193 BR_V)
194#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
195
196/*
197 * Use L1 as initial stack
198 */
199#define CONFIG_SYS_INIT_RAM_LOCK 1
200#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
201#define CONFIG_SYS_INIT_RAM_END 0x00004000
202
203#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
204#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
205#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
206
207#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
208#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
209
210/*
211 * Serial Port
212 */
213#define CONFIG_CONS_INDEX 1
214#define CONFIG_SYS_NS16550
215#define CONFIG_SYS_NS16550_SERIAL
216#define CONFIG_SYS_NS16550_REG_SIZE 1
217#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
218#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
219#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
220#define CONFIG_SYS_BAUDRATE_TABLE \
221 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
222#define CONFIG_BAUDRATE 115200
223#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
224#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
225
226/*
227 * Use the HUSH parser
228 */
229#define CONFIG_SYS_HUSH_PARSER
230#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
231
232/*
233 * Pass open firmware flat tree
234 */
235#define CONFIG_OF_LIBFDT 1
236#define CONFIG_OF_BOARD_SETUP 1
237#define CONFIG_OF_STDOUT_VIA_ALIAS 1
238
239#define CONFIG_SYS_64BIT_VSPRINTF 1
240#define CONFIG_SYS_64BIT_STRTOUL 1
241
242/*
243 * I2C
244 */
245#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
246#define CONFIG_HARD_I2C /* I2C with hardware support */
247#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
248#define CONFIG_SYS_I2C_SLAVE 0x7F
249#define CONFIG_SYS_I2C_OFFSET 0x3000
250#define CONFIG_SYS_I2C2_OFFSET 0x3100
251#define CONFIG_I2C_MULTI_BUS
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]252
253/* PEX8518 slave I2C interface */
254#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
255
256/* I2C DS1631 temperature sensor */
257#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
258#define CONFIG_DTT_DS1621
259#define CONFIG_DTT_SENSORS { 0 }
260
261/* I2C EEPROM - AT24C128B */
262#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
263#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
264#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
265#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
266
267/* I2C RTC */
268#define CONFIG_RTC_M41T11 1
269#define CONFIG_SYS_I2C_RTC_ADDR 0x68
270#define CONFIG_SYS_M41T11_BASE_YEAR 2000
271
272/* GPIO/EEPROM/SRAM */
273#define CONFIG_DS4510
274#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
275
276/* GPIO */
277#define CONFIG_PCA953X
278#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
279#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
280#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
281#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
282#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
283
284/*
285 * PU = pulled high, PD = pulled low
286 * I = input, O = output, IO = input/output
287 */
288/* PCA9557 @ 0x18*/
289#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
290#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
291#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
292#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
293#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
294#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
295#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
296#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
297
298/* PCA9557 @ 0x1c*/
299#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
300#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
301#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
302#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
303#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
304#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
305#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
306#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
307
308/* PCA9557 @ 0x1e*/
309#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
310#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
311#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
312#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
313#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
314#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
315#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
316
317/* PCA9557 @ 0x1f */
318#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
319#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
320#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
321#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
322#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
323
324/*
325 * General PCI
326 * Memory space is mapped 1-1, but I/O space must start from 0.
327 */
328/* PCIE1 - VPX P1 */
329#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
330#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
331#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
332#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
333#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
334#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
335
336/* PCIE2 - PEX8518 */
337#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
338#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
339#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
340#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
341#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
342#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
343
344/*
345 * Networking options
346 */
347#define CONFIG_TSEC_ENET /* tsec ethernet support */
348#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
349#define CONFIG_NET_MULTI 1
350#define CONFIG_TSEC_TBI
351#define CONFIG_MII 1 /* MII PHY management */
352#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
353#define CONFIG_ETHPRIME "eTSEC2"
354
355#define CONFIG_TSEC1 1
356#define CONFIG_TSEC1_NAME "eTSEC1"
357#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
358#define TSEC1_PHY_ADDR 1
359#define TSEC1_PHYIDX 0
360#define CONFIG_HAS_ETH0
361
362#define CONFIG_TSEC2 1
363#define CONFIG_TSEC2_NAME "eTSEC2"
364#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
365#define TSEC2_PHY_ADDR 2
366#define TSEC2_PHYIDX 0
367#define CONFIG_HAS_ETH1
368
369/*
370 * Command configuration.
371 */
372#include <config_cmd_default.h>
373
374#define CONFIG_CMD_ASKENV
375#define CONFIG_CMD_DATE
376#define CONFIG_CMD_DHCP
377#define CONFIG_CMD_DS4510
378#define CONFIG_CMD_DS4510_INFO
379#define CONFIG_CMD_DTT
380#define CONFIG_CMD_EEPROM
381#define CONFIG_CMD_ELF
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]382#define CONFIG_CMD_FLASH
383#define CONFIG_CMD_I2C
384#define CONFIG_CMD_JFFS2
385#define CONFIG_CMD_MII
Peter Tyser95947f92009-07-21 13:51:08 -0500[diff] [blame]386#define CONFIG_CMD_NAND
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]387#define CONFIG_CMD_NET
388#define CONFIG_CMD_PCA953X
389#define CONFIG_CMD_PCA953X_INFO
390#define CONFIG_CMD_PCI
391#define CONFIG_CMD_PING
Peter Tyser95947f92009-07-21 13:51:08 -0500[diff] [blame]392#define CONFIG_CMD_SAVEENV
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]393#define CONFIG_CMD_SNTP
394
395/*
396 * Miscellaneous configurable options
397 */
398#define CONFIG_SYS_LONGHELP /* undef to save memory */
399#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
400#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
401#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
402#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
403#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
404#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
405#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
406#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
407#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
408#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
409#define CONFIG_PANIC_HANG /* do not reset board on panic */
410#define CONFIG_PREBOOT /* enable preboot variable */
411#define CONFIG_FIT 1
412#define CONFIG_FIT_VERBOSE 1
413#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
414
415/*
416 * For booting Linux, the board info and command line data
417 * have to be in the first 16 MB of memory, since this is
418 * the maximum mapped by the Linux kernel during initialization.
419 */
420#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser3744c402009-07-21 13:51:07 -0500[diff] [blame]421#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyser1c2b3292008-12-17 16:36:23 -0600[diff] [blame]422
423/*
424 * Boot Flags
425 */
426#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
427#define BOOTFLAG_WARM 0x02 /* Software reboot */
428
429/*
430 * Environment Configuration
431 */
432#define CONFIG_ENV_IS_IN_FLASH 1
433#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
434#define CONFIG_ENV_SIZE 0x8000
435#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
436
437/*
438 * Flash memory map:
439 * fff80000 - ffffffff Pri U-Boot (512 KB)
440 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
441 * fff00000 - fff3ffff Pri FDT (256KB)
442 * fef00000 - ffefffff Pri OS image (16MB)
443 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
444 *
445 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
446 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
447 * f7f00000 - f7f3ffff Sec FDT (256KB)
448 * f6f00000 - f7efffff Sec OS image (16MB)
449 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
450 */
451#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
452#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
453#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
454#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
455#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
456#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
457
458#define CONFIG_PROG_UBOOT1 \
459 "$download_cmd $loadaddr $ubootfile; " \
460 "if test $? -eq 0; then " \
461 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
462 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
463 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
464 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
465 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
466 "if test $? -ne 0; then " \
467 "echo PROGRAM FAILED; " \
468 "else; " \
469 "echo PROGRAM SUCCEEDED; " \
470 "fi; " \
471 "else; " \
472 "echo DOWNLOAD FAILED; " \
473 "fi;"
474
475#define CONFIG_PROG_UBOOT2 \
476 "$download_cmd $loadaddr $ubootfile; " \
477 "if test $? -eq 0; then " \
478 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
479 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
480 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
481 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
482 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
483 "if test $? -ne 0; then " \
484 "echo PROGRAM FAILED; " \
485 "else; " \
486 "echo PROGRAM SUCCEEDED; " \
487 "fi; " \
488 "else; " \
489 "echo DOWNLOAD FAILED; " \
490 "fi;"
491
492#define CONFIG_BOOT_OS_NET \
493 "$download_cmd $osaddr $osfile; " \
494 "if test $? -eq 0; then " \
495 "if test -n $fdtaddr; then " \
496 "$download_cmd $fdtaddr $fdtfile; " \
497 "if test $? -eq 0; then " \
498 "bootm $osaddr - $fdtaddr; " \
499 "else; " \
500 "echo FDT DOWNLOAD FAILED; " \
501 "fi; " \
502 "else; " \
503 "bootm $osaddr; " \
504 "fi; " \
505 "else; " \
506 "echo OS DOWNLOAD FAILED; " \
507 "fi;"
508
509#define CONFIG_PROG_OS1 \
510 "$download_cmd $osaddr $osfile; " \
511 "if test $? -eq 0; then " \
512 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
513 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
514 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
515 "if test $? -ne 0; then " \
516 "echo OS PROGRAM FAILED; " \
517 "else; " \
518 "echo OS PROGRAM SUCCEEDED; " \
519 "fi; " \
520 "else; " \
521 "echo OS DOWNLOAD FAILED; " \
522 "fi;"
523
524#define CONFIG_PROG_OS2 \
525 "$download_cmd $osaddr $osfile; " \
526 "if test $? -eq 0; then " \
527 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
528 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
529 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
530 "if test $? -ne 0; then " \
531 "echo OS PROGRAM FAILED; " \
532 "else; " \
533 "echo OS PROGRAM SUCCEEDED; " \
534 "fi; " \
535 "else; " \
536 "echo OS DOWNLOAD FAILED; " \
537 "fi;"
538
539#define CONFIG_PROG_FDT1 \
540 "$download_cmd $fdtaddr $fdtfile; " \
541 "if test $? -eq 0; then " \
542 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
543 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
544 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
545 "if test $? -ne 0; then " \
546 "echo FDT PROGRAM FAILED; " \
547 "else; " \
548 "echo FDT PROGRAM SUCCEEDED; " \
549 "fi; " \
550 "else; " \
551 "echo FDT DOWNLOAD FAILED; " \
552 "fi;"
553
554#define CONFIG_PROG_FDT2 \
555 "$download_cmd $fdtaddr $fdtfile; " \
556 "if test $? -eq 0; then " \
557 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
558 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
559 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
560 "if test $? -ne 0; then " \
561 "echo FDT PROGRAM FAILED; " \
562 "else; " \
563 "echo FDT PROGRAM SUCCEEDED; " \
564 "fi; " \
565 "else; " \
566 "echo FDT DOWNLOAD FAILED; " \
567 "fi;"
568
569#define CONFIG_EXTRA_ENV_SETTINGS \
570 "autoload=yes\0" \
571 "download_cmd=tftp\0" \
572 "console_args=console=ttyS0,115200\0" \
573 "root_args=root=/dev/nfs rw\0" \
574 "misc_args=ip=on\0" \
575 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
576 "bootfile=/home/user/file\0" \
577 "osfile=/home/user/uImage-XPedite5370\0" \
578 "fdtfile=/home/user/xpedite5370.dtb\0" \
579 "ubootfile=/home/user/u-boot.bin\0" \
580 "fdtaddr=c00000\0" \
581 "osaddr=0x1000000\0" \
582 "loadaddr=0x1000000\0" \
583 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
584 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
585 "prog_os1="CONFIG_PROG_OS1"\0" \
586 "prog_os2="CONFIG_PROG_OS2"\0" \
587 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
588 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
589 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
590 "bootcmd_flash1=run set_bootargs; " \
591 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
592 "bootcmd_flash2=run set_bootargs; " \
593 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
594 "bootcmd=run bootcmd_flash1\0"
595#endif /* __CONFIG_H */