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Michal Simek0dd222b2013-04-22 14:56:49 +02001/*
Michal Simek9ecd2682015-11-30 16:13:03 +01002 * (C) Copyright 2013 - 2015 Xilinx, Inc.
Michal Simek0dd222b2013-04-22 14:56:49 +02003 *
4 * Xilinx Zynq SD Host Controller Interface
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Michal Simek0dd222b2013-04-22 14:56:49 +02007 */
8
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +01009#include <clk.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020010#include <common.h>
Michal Simek9ecd2682015-11-30 16:13:03 +010011#include <dm.h>
Michal Simekc57ba042014-02-24 11:16:31 +010012#include <fdtdec.h>
13#include <libfdt.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020014#include <malloc.h>
15#include <sdhci.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020016
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +010017DECLARE_GLOBAL_DATA_PTR;
18
Siva Durga Prasad Paladuguf02a5e22016-01-05 12:21:04 +053019#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
20# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
21#endif
22
Simon Glass4cc87fb2016-07-05 17:10:15 -060023struct arasan_sdhci_plat {
24 struct mmc_config cfg;
25 struct mmc mmc;
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +010026 unsigned int f_max;
Simon Glass4cc87fb2016-07-05 17:10:15 -060027};
28
Michal Simek9ecd2682015-11-30 16:13:03 +010029static int arasan_sdhci_probe(struct udevice *dev)
Michal Simek0dd222b2013-04-22 14:56:49 +020030{
Simon Glass4cc87fb2016-07-05 17:10:15 -060031 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Michal Simek9ecd2682015-11-30 16:13:03 +010032 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
33 struct sdhci_host *host = dev_get_priv(dev);
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +010034 struct clk clk;
35 unsigned long clock;
Simon Glass4cc87fb2016-07-05 17:10:15 -060036 int ret;
Michal Simek0dd222b2013-04-22 14:56:49 +020037
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +010038 ret = clk_get_by_index(dev, 0, &clk);
39 if (ret < 0) {
40 dev_err(dev, "failed to get clock\n");
41 return ret;
42 }
43
44 clock = clk_get_rate(&clk);
45 if (IS_ERR_VALUE(clock)) {
46 dev_err(dev, "failed to get rate\n");
47 return clock;
48 }
49 debug("%s: CLK %ld\n", __func__, clock);
50
51 ret = clk_enable(&clk);
52 if (ret && ret != -ENOSYS) {
53 dev_err(dev, "failed to enable clock\n");
54 return ret;
55 }
56
Siva Durga Prasad Paladugu049e0032014-07-08 15:31:04 +053057 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
Siva Durga Prasad Paladugu0d6891b2014-01-22 09:17:09 +010058 SDHCI_QUIRK_BROKEN_R1B;
Siva Durga Prasad Paladugua1619fe2016-01-12 15:12:16 +053059
60#ifdef CONFIG_ZYNQ_HISPD_BROKEN
61 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
62#endif
63
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +010064 host->max_clk = clock;
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +010065
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +010066 ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +090067 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
Simon Glass4cc87fb2016-07-05 17:10:15 -060068 host->mmc = &plat->mmc;
69 if (ret)
70 return ret;
71 host->mmc->priv = host;
Simon Glass77ca42b2016-05-01 13:52:34 -060072 host->mmc->dev = dev;
Simon Glass4cc87fb2016-07-05 17:10:15 -060073 upriv->mmc = host->mmc;
Michal Simek9ecd2682015-11-30 16:13:03 +010074
Simon Glass4cc87fb2016-07-05 17:10:15 -060075 return sdhci_probe(dev);
Michal Simek0dd222b2013-04-22 14:56:49 +020076}
Michal Simek9ecd2682015-11-30 16:13:03 +010077
78static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
79{
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +010080 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Michal Simek9ecd2682015-11-30 16:13:03 +010081 struct sdhci_host *host = dev_get_priv(dev);
82
Masahiro Yamadaa4405612016-04-22 20:59:31 +090083 host->name = dev->name;
Michal Simek9ecd2682015-11-30 16:13:03 +010084 host->ioaddr = (void *)dev_get_addr(dev);
85
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +010086 plat->f_max = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
87 "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
88
Michal Simek9ecd2682015-11-30 16:13:03 +010089 return 0;
90}
91
Simon Glass4cc87fb2016-07-05 17:10:15 -060092static int arasan_sdhci_bind(struct udevice *dev)
93{
94 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Simon Glass4cc87fb2016-07-05 17:10:15 -060095
Masahiro Yamadacdb67f32016-09-06 22:17:32 +090096 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glass4cc87fb2016-07-05 17:10:15 -060097}
98
Michal Simek9ecd2682015-11-30 16:13:03 +010099static const struct udevice_id arasan_sdhci_ids[] = {
100 { .compatible = "arasan,sdhci-8.9a" },
101 { }
102};
103
104U_BOOT_DRIVER(arasan_sdhci_drv) = {
105 .name = "arasan_sdhci",
106 .id = UCLASS_MMC,
107 .of_match = arasan_sdhci_ids,
108 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
Simon Glass4cc87fb2016-07-05 17:10:15 -0600109 .ops = &sdhci_ops,
110 .bind = arasan_sdhci_bind,
Michal Simek9ecd2682015-11-30 16:13:03 +0100111 .probe = arasan_sdhci_probe,
112 .priv_auto_alloc_size = sizeof(struct sdhci_host),
Simon Glass4cc87fb2016-07-05 17:10:15 -0600113 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
Michal Simek9ecd2682015-11-30 16:13:03 +0100114};