Suman Anna | 3eb2b45 | 2019-09-04 16:01:33 +0530 | [diff] [blame] | 1 | TI K3 R5F processor subsystems |
| 2 | ============================== |
| 3 | |
| 4 | The TI K3 family of SoCs usually have one or more dual-core Arm Cortex |
| 5 | R5F processor subsystems/clusters (R5FSS). The dual core cluster can be |
| 6 | used either in a LockStep mode providing safety/fault tolerance features |
| 7 | or in a Split mode providing two individual compute cores for doubling |
| 8 | the compute capacity. These are used together with other processors |
| 9 | present on the SoC to achieve various system level goals. |
| 10 | |
| 11 | R5F Sub-System Device Node: |
| 12 | =========================== |
| 13 | Each Dual-Core R5F sub-system is represented as a single DTS node representing |
| 14 | the cluster, with a pair of child DT nodes representing the individual R5F |
| 15 | cores. Each node has a number of required or optional properties that enable |
| 16 | the OS running on the host processor to perform the device management of the |
| 17 | remote processor and to communicate with the remote processor. |
| 18 | |
| 19 | Required properties: |
| 20 | -------------------- |
| 21 | The following are the mandatory properties: |
| 22 | |
| 23 | - compatible: Should be one of the following, |
| 24 | "ti,am654-r5fss" for R5F clusters/subsystems on |
| 25 | K3 AM65x SoCs |
| 26 | "ti,j721e-r5fss" for R5F clusters/subsystems on |
| 27 | K3 J721E SoCs |
| 28 | - power-domains: Should contain a phandle to a PM domain provider node |
| 29 | and an args specifier containing the R5FSS device id |
| 30 | value. This property is as per the binding, |
| 31 | Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt |
| 32 | - #address-cells: Should be 1 |
| 33 | - #size-cells: Should be 1 |
| 34 | - ranges: Standard ranges definition providing translations for |
| 35 | R5F TCM address spaces |
| 36 | |
| 37 | Optional properties: |
| 38 | -------------------- |
| 39 | - lockstep-mode: Configuration Mode for the Dual R5F cores within the R5F |
| 40 | cluster. Should be either a value of 1 (LockStep mode) or |
| 41 | 0 (Split mode), default is LockStep mode if omitted. |
| 42 | |
| 43 | |
| 44 | R5F Processor Child Nodes: |
| 45 | ========================== |
| 46 | The R5F Sub-System device node should define two R5F child nodes, each node |
| 47 | representing a TI instantiation of the Arm Cortex R5F core. There are some |
| 48 | specific integration differences for the IP like the usage of a Region Address |
| 49 | Translator (RAT) for translating the larger SoC bus addresses into a 32-bit |
| 50 | address space for the processor. |
| 51 | |
| 52 | Required properties: |
| 53 | -------------------- |
| 54 | The following are the mandatory properties: |
| 55 | |
| 56 | - compatible: Should be one of the following, |
| 57 | "ti,am654-r5f" for the R5F cores in K3 AM65x SoCs |
| 58 | "ti,j721e-r5f" for the R5F cores in K3 J721E SOCs |
| 59 | - reg: Should contain an entry for each value in 'reg-names'. |
| 60 | Each entry should have the memory region's start address |
| 61 | and the size of the region, the representation matching |
| 62 | the parent node's '#address-cells' and '#size-cells' values. |
| 63 | - reg-names: Should contain strings with the following names, each |
| 64 | representing a specific internal memory region, and |
| 65 | should be defined in this order, |
| 66 | "atcm", "btcm" |
| 67 | - ti,sci: Should be a phandle to the TI-SCI System Controller node |
| 68 | - ti,sci-dev-id: Should contain the TI-SCI device id corresponding to the |
| 69 | R5F Core. Please refer to the corresponding System |
| 70 | Controller documentation for valid values for the R5F |
| 71 | cores. |
| 72 | - ti,sci-proc-ids: Should contain 2 integer values. The first cell should |
| 73 | contain the TI-SCI processor id for the R5F core device |
| 74 | and the second cell should contain the TI-SCI host id to |
| 75 | which the processor control ownership should be |
| 76 | transferred to. |
| 77 | - resets: Should contain the phandle to the reset controller node |
| 78 | managing the resets for this device, and a reset |
| 79 | specifier. Please refer to the following reset bindings |
| 80 | for the reset argument specifier, |
| 81 | Documentation/devicetree/bindings/reset/ti,sci-reset.txt |
| 82 | for AM65x and J721E SoCs |
| 83 | |
| 84 | Optional properties: |
| 85 | -------------------- |
| 86 | The following properties are optional properties for each of the R5F cores: |
| 87 | |
| 88 | - atcm-enable: R5F core configuration mode dictating if ATCM should be |
| 89 | enabled. Should be either a value of 1 (enabled) or |
| 90 | 0 (disabled), default is disabled if omitted. R5F view |
| 91 | of ATCM dictated by loczrama property. |
| 92 | - btcm-enable: R5F core configuration mode dictating if BTCM should be |
| 93 | enabled. Should be either a value of 1 (enabled) or |
| 94 | 0 (disabled), default is enabled if omitted. R5F view |
| 95 | of BTCM dictated by loczrama property. |
| 96 | - loczrama: R5F core configuration mode dictating which TCM should |
| 97 | appear at address 0 (from core's view). Should be either |
| 98 | a value of 1 (ATCM at 0x0) or 0 (BTCM at 0x0), default |
| 99 | value is 1 if omitted. |
| 100 | |
| 101 | Example: |
| 102 | -------- |
| 103 | 1. AM654 SoC |
| 104 | /* AM65x remoteproc alias */ |
| 105 | aliases { |
| 106 | remoteproc0 = &mcu_r5fss0_core0; |
| 107 | }; |
| 108 | |
| 109 | cbass_main: interconnect@100000 { |
| 110 | compatible = "simple-bus"; |
| 111 | #address-cells = <2>; |
| 112 | #size-cells = <2>; |
| 113 | ranges = <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, |
| 114 | <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, |
| 115 | <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; |
| 116 | |
| 117 | cbass_mcu: interconnect@28380000 { |
| 118 | compatible = "simple-bus"; |
| 119 | #address-cells = <2>; |
| 120 | #size-cells = <2>; |
| 121 | ranges = <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ |
| 122 | <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ |
| 123 | <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */ |
| 124 | |
| 125 | /* AM65x MCU R5FSS node */ |
| 126 | mcu_r5fss0: r5fss@41000000 { |
| 127 | compatible = "ti,am654-r5fss"; |
| 128 | power-domains = <&k3_pds 129>; |
| 129 | lockstep-mode = <1>; |
| 130 | #address-cells = <1>; |
| 131 | #size-cells = <1>; |
| 132 | ranges = <0x41000000 0x00 0x41000000 0x20000>, |
| 133 | <0x41400000 0x00 0x41400000 0x20000>; |
| 134 | |
| 135 | mcu_r5f0: r5f@41000000 { |
| 136 | compatible = "ti,am654-r5f"; |
| 137 | reg = <0x41000000 0x00008000>, |
| 138 | <0x41010000 0x00008000>; |
| 139 | reg-names = "atcm", "btcm"; |
| 140 | ti,sci = <&dmsc>; |
| 141 | ti,sci-dev-id = <159>; |
| 142 | ti,sci-proc-ids = <0x01 0xFF>; |
| 143 | resets = <&k3_reset 159 1>; |
| 144 | atcm-enable = <1>; |
| 145 | btcm-enable = <1>; |
| 146 | loczrama = <1>; |
| 147 | }; |
| 148 | |
| 149 | mcu_r5f1: r5f@41400000 { |
| 150 | compatible = "ti,am654-r5f"; |
| 151 | reg = <0x41400000 0x00008000>, |
| 152 | <0x41410000 0x00008000>; |
| 153 | reg-names = "atcm", "btcm"; |
| 154 | ti,sci = <&dmsc>; |
| 155 | ti,sci-dev-id = <245>; |
| 156 | ti,sci-proc-ids = <0x02 0xFF>; |
| 157 | resets = <&k3_reset 245 1>; |
| 158 | atcm-enable = <1>; |
| 159 | btcm-enable = <1>; |
| 160 | loczrama = <1>; |
| 161 | }; |
| 162 | }; |
| 163 | }; |
| 164 | }; |