| Wenyou Yang | 5a09d13 | 2015-11-04 14:25:13 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Atmel Corporation. |
| 3 | * Wenyou Yang <wenyou.yang@atmel.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef __ATMEL_PIO4_H |
| 9 | #define __ATMEL_PIO4_H |
| 10 | |
| 11 | #ifndef __ASSEMBLY__ |
| 12 | |
| 13 | struct atmel_pio4_port { |
| 14 | u32 mskr; /* 0x00 PIO Mask Register */ |
| 15 | u32 cfgr; /* 0x04 PIO Configuration Register */ |
| 16 | u32 pdsr; /* 0x08 PIO Pin Data Status Register */ |
| 17 | u32 locksr; /* 0x0C PIO Lock Status Register */ |
| 18 | u32 sodr; /* 0x10 PIO Set Output Data Register */ |
| 19 | u32 codr; /* 0x14 PIO Clear Output Data Register */ |
| 20 | u32 odsr; /* 0x18 PIO Output Data Status Register */ |
| 21 | u32 reserved0; |
| 22 | u32 ier; /* 0x20 PIO Interrupt Enable Register */ |
| 23 | u32 idr; /* 0x24 PIO Interrupt Disable Register */ |
| 24 | u32 imr; /* 0x28 PIO Interrupt Mask Register */ |
| 25 | u32 isr; /* 0x2C PIO Interrupt Status Register */ |
| 26 | u32 reserved1[3]; |
| 27 | u32 iofr; /* 0x3C PIO I/O Freeze Register */ |
| 28 | }; |
| 29 | |
| 30 | #endif |
| 31 | |
| Wenyou Yang | 312bf89 | 2016-07-20 17:16:25 +0800 | [diff] [blame] | 32 | /* |
| 33 | * PIO Configuration Register Fields |
| 34 | */ |
| 35 | #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) |
| 36 | #define ATMEL_PIO_CFGR_FUNC_GPIO (0x0 << 0) |
| 37 | #define ATMEL_PIO_CFGR_FUNC_PERIPH_A (0x1 << 0) |
| 38 | #define ATMEL_PIO_CFGR_FUNC_PERIPH_B (0x2 << 0) |
| 39 | #define ATMEL_PIO_CFGR_FUNC_PERIPH_C (0x3 << 0) |
| 40 | #define ATMEL_PIO_CFGR_FUNC_PERIPH_D (0x4 << 0) |
| 41 | #define ATMEL_PIO_CFGR_FUNC_PERIPH_E (0x5 << 0) |
| 42 | #define ATMEL_PIO_CFGR_FUNC_PERIPH_F (0x6 << 0) |
| 43 | #define ATMEL_PIO_CFGR_FUNC_PERIPH_G (0x7 << 0) |
| 44 | #define ATMEL_PIO_DIR_MASK BIT(8) |
| 45 | #define ATMEL_PIO_PUEN_MASK BIT(9) |
| 46 | #define ATMEL_PIO_PDEN_MASK BIT(10) |
| 47 | #define ATMEL_PIO_IFEN_MASK BIT(12) |
| 48 | #define ATMEL_PIO_IFSCEN_MASK BIT(13) |
| 49 | #define ATMEL_PIO_OPD_MASK BIT(14) |
| 50 | #define ATMEL_PIO_SCHMITT_MASK BIT(15) |
| 51 | #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) |
| 52 | #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) |
| 53 | #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) |
| 54 | #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) |
| 55 | #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) |
| 56 | #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) |
| 57 | |
| 58 | #define ATMEL_PIO_NPINS_PER_BANK 32 |
| 59 | #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) |
| 60 | #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) |
| 61 | #define ATMEL_PIO_BANK_OFFSET 0x40 |
| 62 | |
| 63 | #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) |
| 64 | #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) |
| 65 | #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) |
| 66 | |
| Wenyou Yang | 5a09d13 | 2015-11-04 14:25:13 +0800 | [diff] [blame] | 67 | #define AT91_PIO_PORTA 0x0 |
| 68 | #define AT91_PIO_PORTB 0x1 |
| 69 | #define AT91_PIO_PORTC 0x2 |
| 70 | #define AT91_PIO_PORTD 0x3 |
| 71 | |
| 72 | int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup); |
| 73 | int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup); |
| 74 | int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup); |
| 75 | int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup); |
| 76 | int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup); |
| 77 | int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup); |
| 78 | int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup); |
| 79 | int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup); |
| 80 | int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value); |
| 81 | int atmel_pio4_get_pio_input(u32 port, u32 pin); |
| 82 | |
| 83 | #endif |