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git01.mediatek.com / filogic / uboot / cad56718089e0cf5f1fb7d398c70454ea1f4d45e / . / arch / m68k / include / asm / immap.h
blob: 74516cc6219920f59e02125d1527082bc51cb956 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]2/*
3 * ColdFire Internal Memory Map and Defines
4 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]5 * Copyright 2004-2012 Freescale Semiconductor, Inc.
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]7 */
8
9#ifndef __IMMAP_H
10#define __IMMAP_H
Stefan Roesef1110122007-07-16 13:11:12 +0200[diff] [blame]11
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]12#if defined(CONFIG_MCF520x)
13#include <asm/immap_520x.h>
14#include <asm/m520x.h>
15
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]16#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]17
18/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]19#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]20#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
21#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
22#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
23#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
24#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
25#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
26#define CFG_SYS_TMRINTR_PRI (6)
27#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]28#endif
29
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]30#define CFG_SYS_INTR_BASE (MMAP_INTC0)
31#define CFG_SYS_NUM_IRQS (128)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]32#endif /* CONFIG_M520x */
33
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]34#ifdef CONFIG_M5235
35#include <asm/immap_5235.h>
36#include <asm/m5235.h>
37
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]38#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]39
40/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]41#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]42#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
43#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
44#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
45#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
46#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
47#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
48#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
49#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]50#endif
51
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]52#define CFG_SYS_INTR_BASE (MMAP_INTC0)
53#define CFG_SYS_NUM_IRQS (128)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]54#endif /* CONFIG_M5235 */
55
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]56#ifdef CONFIG_M5249
57#include <asm/immap_5249.h>
58#include <asm/m5249.h>
59
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]60#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]61
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]62#define CFG_SYS_INTR_BASE (MMAP_INTC)
63#define CFG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]64
65/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]66#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]67#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
68#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
69#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
70#define CFG_SYS_TMRINTR_NO (31)
71#define CFG_SYS_TMRINTR_MASK (0x00000400)
72#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
73#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
74#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]75#endif
76#endif /* CONFIG_M5249 */
77
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]78#ifdef CONFIG_M5253
79#include <asm/immap_5253.h>
80#include <asm/m5249.h>
81#include <asm/m5253.h>
82
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]83#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]84
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]85#define CFG_SYS_INTR_BASE (MMAP_INTC)
86#define CFG_SYS_NUM_IRQS (64)
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]87
88/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]89#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]90#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
91#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
92#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
93#define CFG_SYS_TMRINTR_NO (27)
94#define CFG_SYS_TMRINTR_MASK (0x00000400)
95#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
96#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
97#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]98#endif
99#endif /* CONFIG_M5253 */
100
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]101#ifdef CONFIG_M5271
102#include <asm/immap_5271.h>
103#include <asm/m5271.h>
104
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]105#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]106
107/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]108#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]109#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
110#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
111#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
112#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
113#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
114#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
115#define CFG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
116#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]117#endif
118
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]119#define CFG_SYS_INTR_BASE (MMAP_INTC0)
120#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]121#endif /* CONFIG_M5271 */
122
123#ifdef CONFIG_M5272
124#include <asm/immap_5272.h>
125#include <asm/m5272.h>
126
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]127#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]128
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]129#define CFG_SYS_INTR_BASE (MMAP_INTC)
130#define CFG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]131
132/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]133#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]134#define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
135#define CFG_SYS_TMR_BASE (MMAP_TMR3)
136#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
137#define CFG_SYS_TMRINTR_NO (INT_TMR3)
138#define CFG_SYS_TMRINTR_MASK (INT_ISR_INT24)
139#define CFG_SYS_TMRINTR_PEND (0)
140#define CFG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
141#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]142#endif
143#endif /* CONFIG_M5272 */
144
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]145#ifdef CONFIG_M5275
146#include <asm/immap_5275.h>
147#include <asm/m5275.h>
148
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]149#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]150
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]151#define CFG_SYS_INTR_BASE (MMAP_INTC0)
152#define CFG_SYS_NUM_IRQS (192)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]153
154/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]155#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]156#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
157#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
158#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
159#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
160#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
161#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
162#define CFG_SYS_TMRINTR_PRI (0x1E)
163#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]164#endif
165#endif /* CONFIG_M5275 */
166
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]167#ifdef CONFIG_M5282
168#include <asm/immap_5282.h>
169#include <asm/m5282.h>
170
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]171#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]172
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]173#define CFG_SYS_INTR_BASE (MMAP_INTC0)
174#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]175
176/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]177#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]178#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
179#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
180#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
181#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
182#define CFG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
183#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
184#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
185#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]186#endif
187#endif /* CONFIG_M5282 */
188
angelo@sysam.itbb4ba2c2015-02-12 01:40:00 +0100[diff] [blame]189#ifdef CONFIG_M5307
190#include <asm/immap_5307.h>
191#include <asm/m5307.h>
192
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]193#define CFG_SYS_UART_BASE (MMAP_UART0 + \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]194 (CFG_SYS_UART_PORT * 0x40))
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]195#define CFG_SYS_INTR_BASE (MMAP_INTC)
196#define CFG_SYS_NUM_IRQS (64)
angelo@sysam.itbb4ba2c2015-02-12 01:40:00 +0100[diff] [blame]197
198/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]199#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]200#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
201#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
202#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
203 (CFG_SYS_INTR_BASE))->ipr)
204#define CFG_SYS_TMRINTR_NO (31)
205#define CFG_SYS_TMRINTR_MASK (0x00000400)
206#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
207#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
angelo@sysam.itbb4ba2c2015-02-12 01:40:00 +0100[diff] [blame]208 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]209#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
angelo@sysam.itbb4ba2c2015-02-12 01:40:00 +0100[diff] [blame]210#endif
211#endif /* CONFIG_M5307 */
212
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]213#if defined(CONFIG_MCF5301x)
214#include <asm/immap_5301x.h>
215#include <asm/m5301x.h>
216
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]217#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]218
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]219/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]220#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]221#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
222#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
223#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
224#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
225#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
226#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
227#define CFG_SYS_TMRINTR_PRI (6)
228#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]229#endif
230
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]231#define CFG_SYS_INTR_BASE (MMAP_INTC0)
232#define CFG_SYS_NUM_IRQS (128)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]233#endif /* CONFIG_M5301x */
234
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600[diff] [blame]235#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]236#include <asm/immap_5329.h>
237#include <asm/m5329.h>
238
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]239#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]240
241/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]242#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]243#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
244#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
245#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
246#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
247#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
248#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
249#define CFG_SYS_TMRINTR_PRI (6)
250#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]251#endif
252
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]253#define CFG_SYS_INTR_BASE (MMAP_INTC0)
254#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600[diff] [blame]255#endif /* CONFIG_M5329 && CONFIG_M5373 */
Stefan Roesef1110122007-07-16 13:11:12 +0200[diff] [blame]256
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]257#if defined(CONFIG_M54418)
258#include <asm/immap_5441x.h>
259#include <asm/m5441x.h>
260
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]261#if (CFG_SYS_UART_PORT < 4)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]262#define CFG_SYS_UART_BASE (MMAP_UART0 + \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]263 (CFG_SYS_UART_PORT * 0x4000))
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]264#else
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]265#define CFG_SYS_UART_BASE (MMAP_UART4 + \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]266 ((CFG_SYS_UART_PORT - 4) * 0x4000))
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]267#endif
268
269#define MMAP_DSPI MMAP_DSPI0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]270
271/* Timer */
Angelo Dureghello49becce2023-02-25 23:25:26 +0100[diff] [blame]272#ifdef CFG_MCFTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]273#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
274#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
275#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
276#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
277#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
278#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
279#define CFG_SYS_TMRINTR_PRI (6)
280#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]281#endif
282
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]283#define CFG_SYS_INTR_BASE (MMAP_INTC0)
284#define CFG_SYS_NUM_IRQS (192)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]285
286#endif /* CONFIG_M54418 */
287
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]288#ifdef CONFIG_M547x
289#include <asm/immap_547x_8x.h>
290#include <asm/m547x_8x.h>
291
292#ifdef CONFIG_FSLDMAFEC
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]293#define FEC0_RX_TASK 0
294#define FEC0_TX_TASK 1
295#define FEC0_RX_PRIORITY 6
296#define FEC0_TX_PRIORITY 7
297#define FEC0_RX_INIT 16
298#define FEC0_TX_INIT 17
299#define FEC1_RX_TASK 2
300#define FEC1_TX_TASK 3
301#define FEC1_RX_PRIORITY 6
302#define FEC1_TX_PRIORITY 7
303#define FEC1_RX_INIT 30
304#define FEC1_TX_INIT 31
305#endif
306
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]307#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]308
309#ifdef CONFIG_SLTTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]310#define CFG_SYS_UDELAY_BASE (MMAP_SLT1)
311#define CFG_SYS_TMR_BASE (MMAP_SLT0)
312#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
313#define CFG_SYS_TMRINTR_NO (INT0_HI_SLT0)
314#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
315#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
316#define CFG_SYS_TMRINTR_PRI (0x1E)
317#define CFG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]318#endif
319
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]320#define CFG_SYS_INTR_BASE (MMAP_INTC0)
321#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]322
323#ifdef CONFIG_PCI
Tom Rini56af6592022-11-16 13:10:33 -0500[diff] [blame]324#define CFG_SYS_PCI_BAR0 (0x40000000)
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]325#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]326#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR)
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]327#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]328#endif
329#endif /* CONFIG_M547x */
330
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]331#endif /* __IMMAP_H */