Kumar Gala | f57f498 | 2008-01-17 01:44:34 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * (C) Copyright 2000 |
| 5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #include <common.h> |
| 27 | #include <asm/mmu.h> |
| 28 | |
| 29 | struct fsl_e_tlb_entry tlb_table[] = { |
| 30 | /* TLB 0 - for temp stack in cache */ |
| 31 | SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
| 32 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 33 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 34 | SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
| 35 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 36 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 37 | SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
| 38 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 39 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 40 | SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
| 41 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 42 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 43 | |
| 44 | /* |
| 45 | * TLB 0: 16M Non-cacheable, guarded |
| 46 | * 0xff800000 16M TLB for 8MB FLASH |
| 47 | * Out of reset this entry is only 4K. |
| 48 | */ |
| 49 | SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
| 50 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 51 | 0, 0, BOOKE_PAGESZ_16M, 1), |
| 52 | |
| 53 | /* |
| 54 | * TLB 1: 256M Non-cacheable, guarded |
| 55 | * 0x80000000 256M PCI1 MEM First half |
| 56 | */ |
| 57 | SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
| 58 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 59 | 0, 1, BOOKE_PAGESZ_256M, 1), |
| 60 | |
| 61 | /* |
| 62 | * TLB 2: 256M Non-cacheable, guarded |
| 63 | * 0x90000000 256M PCI1 MEM Second half |
| 64 | */ |
| 65 | SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
| 66 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 67 | 0, 2, BOOKE_PAGESZ_256M, 1), |
| 68 | |
| 69 | /* |
| 70 | * TLB 3: 256M Cacheable, non-guarded |
| 71 | * 0x0 256M DDR SDRAM |
| 72 | */ |
| 73 | #if !defined(CONFIG_SPD_EEPROM) |
| 74 | SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
| 75 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 76 | 0, 3, BOOKE_PAGESZ_256M, 1), |
| 77 | #endif |
| 78 | |
| 79 | /* |
| 80 | * TLB 4: 64M Non-cacheable, guarded |
| 81 | * 0xe0000000 1M CCSRBAR |
| 82 | * 0xe2000000 16M PCI1 IO |
| 83 | */ |
Kumar Gala | d33a55f | 2008-01-30 14:55:14 -0600 | [diff] [blame] | 84 | SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, |
Kumar Gala | f57f498 | 2008-01-17 01:44:34 -0600 | [diff] [blame] | 85 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 86 | 0, 4, BOOKE_PAGESZ_64M, 1), |
| 87 | |
| 88 | /* |
| 89 | * TLB 5: 64M Cacheable, non-guarded |
| 90 | * 0xf0000000 64M LBC SDRAM |
| 91 | */ |
| 92 | SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
| 93 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 94 | 0, 5, BOOKE_PAGESZ_64M, 1), |
| 95 | |
| 96 | /* |
| 97 | * TLB 6: 16M Cacheable, non-guarded |
| 98 | * 0xf8000000 1M 7-segment LED display |
| 99 | * 0xf8100000 1M User switches |
| 100 | * 0xf8300000 1M Board revision |
| 101 | * 0xf8b00000 1M EEPROM |
| 102 | */ |
| 103 | SET_TLB_ENTRY(1, CFG_EPLD_BASE, CFG_EPLD_BASE, |
| 104 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 105 | 0, 6, BOOKE_PAGESZ_16M, 1), |
| 106 | }; |
| 107 | |
| 108 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |