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git01.mediatek.com / filogic / uboot / cad18b87ed93cddacd9976ed9c60cda1475bcea7 / . / arch / arm / dts / exynos5800-peach-pi.dts
blob: e4bc100995c3112b2749f5bf96d4a449debbeaf5 [file] [log] [blame]
Akshay Saraswat257863f2014-11-13 22:38:16 +0530[diff] [blame]1/*
2 * SAMSUNG/GOOGLE Peach-Pit board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10/dts-v1/;
11#include "exynos54xx.dtsi"
12
13/ {
14 model = "Samsung/Google Peach Pi board based on Exynos5800";
15
16 compatible = "google,pit-rev#", "google,pit",
17 "google,peach", "samsung,exynos5800", "samsung,exynos5";
18
19 config {
Simon Glassdabafc32015-01-05 20:05:42 -0700[diff] [blame]20 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
Akshay Saraswat257863f2014-11-13 22:38:16 +0530[diff] [blame]21 hwid = "PIT TEST A-A 7848";
22 lazy-init = <1>;
23 };
24
25 aliases {
26 serial0 = "/serial@12C30000";
27 console = "/serial@12C30000";
28 pmic = "/i2c@12ca0000";
29 };
30
31 dmc {
32 mem-manuf = "samsung";
33 mem-type = "ddr3";
34 clock-frequency = <800000000>;
Simon Glassdabafc32015-01-05 20:05:42 -0700[diff] [blame]35 arm-frequency = <900000000>;
Akshay Saraswat257863f2014-11-13 22:38:16 +0530[diff] [blame]36 };
37
38 tmu@10060000 {
39 samsung,min-temp = <25>;
40 samsung,max-temp = <125>;
41 samsung,start-warning = <95>;
42 samsung,start-tripping = <105>;
43 samsung,hw-tripping = <110>;
44 samsung,efuse-min-value = <40>;
45 samsung,efuse-value = <55>;
46 samsung,efuse-max-value = <100>;
47 samsung,slope = <274761730>;
48 samsung,dc-value = <25>;
49 };
50
51 /* MAX77802 is on i2c bus 4 */
52 i2c@12ca0000 {
53 clock-frequency = <400000>;
54 power-regulator@9 {
55 compatible = "maxim,max77802-pmic";
56 reg = <0x9>;
57 };
58 };
59
60 i2c@12cd0000 { /* i2c7 */
61 clock-frequency = <100000>;
62 soundcodec@20 {
63 reg = <0x20>;
64 compatible = "maxim,max98090-codec";
65 };
Akshay Saraswat257863f2014-11-13 22:38:16 +0530[diff] [blame]66 };
67
68 sound@3830000 {
69 samsung,codec-type = "max98090";
70 };
71
72 i2c@12e10000 { /* i2c9 */
73 clock-frequency = <400000>;
74 tpm@20 {
75 compatible = "infineon,slb9645-tpm";
76 reg = <0x20>;
77 };
78 };
79
80 spi@12d30000 { /* spi1 */
81 spi-max-frequency = <50000000>;
82 firmware_storage_spi: flash@0 {
83 reg = <0>;
84
85 /*
86 * A region for the kernel to store a panic event
87 * which the firmware will add to the log.
88 */
89 elog-panic-event-offset = <0x01e00000 0x100000>;
90
91 elog-shrink-size = <0x400>;
92 elog-full-threshold = <0xc00>;
93 };
94 };
95
96 spi@12d40000 { /* spi2 */
97 spi-max-frequency = <4000000>;
98 spi-deactivate-delay = <200>;
Sjoerd Simonsd2f895f2014-11-27 16:34:08 +0100[diff] [blame]99 cros_ec: cros-ec@0 {
Akshay Saraswat257863f2014-11-13 22:38:16 +0530[diff] [blame]100 reg = <0>;
101 compatible = "google,cros-ec";
102 spi-half-duplex;
103 spi-max-timeout-ms = <1100>;
104 spi-frame-header = <0xec>;
Simon Glassdabafc32015-01-05 20:05:42 -0700[diff] [blame]105 ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
Akshay Saraswat257863f2014-11-13 22:38:16 +0530[diff] [blame]106
107 /*
108 * This describes the flash memory within the EC. Note
109 * that the STM32L flash erases to 0, not 0xff.
110 */
111 #address-cells = <1>;
112 #size-cells = <1>;
113 flash@8000000 {
114 reg = <0x08000000 0x20000>;
115 erase-value = <0>;
116 };
117 };
118 };
119
120 xhci@12000000 {
Simon Glassdabafc32015-01-05 20:05:42 -0700[diff] [blame]121 samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
Akshay Saraswat257863f2014-11-13 22:38:16 +0530[diff] [blame]122 };
123
124 xhci@12400000 {
Simon Glassdabafc32015-01-05 20:05:42 -0700[diff] [blame]125 samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
Akshay Saraswat257863f2014-11-13 22:38:16 +0530[diff] [blame]126 };
127
128 fimd@14400000 {
129 samsung,vl-freq = <60>;
130 samsung,vl-col = <1920>;
131 samsung,vl-row = <1080>;
132 samsung,vl-width = <1920>;
133 samsung,vl-height = <1080>;
134
135 samsung,vl-clkp;
136 samsung,vl-dp;
137 samsung,vl-bpix = <4>;
138
139 samsung,vl-hspw = <80>;
140 samsung,vl-hbpd = <172>;
141 samsung,vl-hfpd = <60>;
142 samsung,vl-vspw = <10>;
143 samsung,vl-vbpd = <25>;
144 samsung,vl-vfpd = <10>;
145 samsung,vl-cmd-allow-len = <0xf>;
146
147 samsung,winid = <3>;
148 samsung,interface-mode = <1>;
149 samsung,dp-enabled = <1>;
150 samsung,dual-lcd-enabled = <0>;
151 };
152};
Sjoerd Simonsd2f895f2014-11-27 16:34:08 +0100[diff] [blame]153
154#include "cros-ec-keyboard.dtsi"