| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. |
| 3 | * (C) Copyright 2007 DENX Software Engineering |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * Derived from the MPC83xx header. |
| 14 | */ |
| 15 | |
| 16 | #ifndef __MPC512X_H__ |
| 17 | #define __MPC512X_H__ |
| 18 | |
| 19 | #include <config.h> |
| 20 | #if defined(CONFIG_E300) |
| 21 | #include <asm/e300.h> |
| 22 | #endif |
| 23 | |
| 24 | /* System reset offset (PowerPC standard) |
| 25 | */ |
| 26 | #define EXC_OFF_SYS_RESET 0x0100 |
| 27 | #define _START_OFFSET EXC_OFF_SYS_RESET |
| 28 | |
| 29 | |
| 30 | /* IMMRBAR - Internal Memory Register Base Address |
| 31 | */ |
| 32 | #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ |
| 33 | #define IMMRBAR 0x0000 /* Register offset to immr */ |
| 34 | #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ |
| 35 | #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) |
| 36 | |
| 37 | /* LAWBAR - Local Access Window Base Address Register |
| 38 | */ |
| 39 | #define LPBAW 0x0020 /* Register offset to immr */ |
| 40 | #define LPCS0AW 0x0024 |
| 41 | #define LPCS1AW 0x0028 |
| 42 | #define LPCS2AW 0x002C |
| 43 | #define LPCS3AW 0x0030 |
| 44 | #define LPCS4AW 0x0034 |
| 45 | #define LPCS5AW 0x0038 |
| 46 | #define LPCS6AW 0x003C |
| 47 | #define LPCA7AW 0x0040 |
| 48 | #define SRAMBAR 0x00C4 |
| John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 49 | #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 50 | |
| 51 | #define LPC_OFFSET 0x10000 |
| 52 | |
| 53 | #define CS0_CONFIG 0x00000 |
| 54 | #define CS1_CONFIG 0x00004 |
| 55 | #define CS2_CONFIG 0x00008 |
| 56 | #define CS3_CONFIG 0x0000C |
| 57 | #define CS4_CONFIG 0x00010 |
| 58 | #define CS5_CONFIG 0x00014 |
| 59 | #define CS6_CONFIG 0x00018 |
| 60 | #define CS7_CONFIG 0x0001C |
| John Rigby | 0c9b301 | 2008-08-28 13:17:07 -0600 | [diff] [blame] | 61 | #define CS_ALE_TIMING_CONFIG 0x00034 |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 62 | |
| 63 | #define CS_CTRL 0x00020 |
| 64 | #define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ |
| Wolfgang Denk | 530181f | 2007-08-02 21:27:46 +0200 | [diff] [blame] | 65 | #define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */ |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 66 | |
| 67 | /* SPRIDR - System Part and Revision ID Register |
| 68 | */ |
| 69 | #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ |
| 70 | #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ |
| 71 | |
| 72 | #define SPR_5121E 0x80180000 |
| 73 | |
| 74 | /* SPCR - System Priority Configuration Register |
| 75 | */ |
| 76 | #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ |
| 77 | #define SPCR_PCIHPE_SHIFT (31-3) |
| 78 | #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ |
| 79 | #define SPCR_PCIPR_SHIFT (31-7) |
| 80 | #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ |
| 81 | #define SPCR_TBEN_SHIFT (31-9) |
| 82 | #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ |
| 83 | #define SPCR_COREPR_SHIFT (31-11) |
| 84 | |
| 85 | /* SWCRR - System Watchdog Control Register |
| 86 | */ |
| 87 | #define SWCRR 0x0904 /* Register offset to immr */ |
| 88 | #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ |
| 89 | #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ |
| 90 | #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ |
| 91 | #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ |
| 92 | #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) |
| 93 | |
| 94 | /* SWCNR - System Watchdog Counter Register |
| 95 | */ |
| 96 | #define SWCNR 0x0908 /* Register offset to immr */ |
| 97 | #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ |
| 98 | #define SWCNR_RES ~(SWCNR_SWCN) |
| 99 | |
| 100 | /* SWSRR - System Watchdog Service Register |
| 101 | */ |
| 102 | #define SWSRR 0x090E /* Register offset to immr */ |
| 103 | |
| 104 | /* ACR - Arbiter Configuration Register |
| 105 | */ |
| 106 | #define ACR_COREDIS 0x10000000 /* Core disable */ |
| 107 | #define ACR_COREDIS_SHIFT (31-7) |
| 108 | #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ |
| 109 | #define ACR_PIPE_DEP_SHIFT (31-15) |
| 110 | #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ |
| 111 | #define ACR_PCI_RPTCNT_SHIFT (31-19) |
| 112 | #define ACR_RPTCNT 0x00000700 /* Repeat count */ |
| 113 | #define ACR_RPTCNT_SHIFT (31-23) |
| 114 | #define ACR_APARK 0x00000030 /* Address parking */ |
| 115 | #define ACR_APARK_SHIFT (31-27) |
| 116 | #define ACR_PARKM 0x0000000F /* Parking master */ |
| 117 | #define ACR_PARKM_SHIFT (31-31) |
| 118 | |
| 119 | /* ATR - Arbiter Timers Register |
| 120 | */ |
| 121 | #define ATR_DTO 0x00FF0000 /* Data time out */ |
| 122 | #define ATR_ATO 0x000000FF /* Address time out */ |
| 123 | |
| 124 | /* AER - Arbiter Event Register |
| 125 | */ |
| 126 | #define AER_ETEA 0x00000020 /* Transfer error */ |
| 127 | #define AER_RES 0x00000010 /* Reserved transfer type */ |
| 128 | #define AER_ECW 0x00000008 /* External control word transfer type */ |
| 129 | #define AER_AO 0x00000004 /* Address Only transfer type */ |
| 130 | #define AER_DTO 0x00000002 /* Data time out */ |
| 131 | #define AER_ATO 0x00000001 /* Address time out */ |
| 132 | |
| 133 | /* AEATR - Arbiter Event Address Register |
| 134 | */ |
| 135 | #define AEATR_EVENT 0x07000000 /* Event type */ |
| 136 | #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ |
| 137 | #define AEATR_TBST 0x00000800 /* Transfer burst */ |
| 138 | #define AEATR_TSIZE 0x00000700 /* Transfer Size */ |
| 139 | #define AEATR_TTYPE 0x0000001F /* Transfer Type */ |
| 140 | |
| 141 | /* RSR - Reset Status Register |
| 142 | */ |
| 143 | #define RSR_SWSR 0x00002000 /* software soft reset */ |
| 144 | #define RSR_SWSR_SHIFT 13 |
| 145 | #define RSR_SWHR 0x00001000 /* software hard reset */ |
| 146 | #define RSR_SWHR_SHIFT 12 |
| 147 | #define RSR_JHRS 0x00000200 /* jtag hreset */ |
| 148 | #define RSR_JHRS_SHIFT 9 |
| 149 | #define RSR_JSRS 0x00000100 /* jtag sreset status */ |
| 150 | #define RSR_JSRS_SHIFT 8 |
| 151 | #define RSR_CSHR 0x00000010 /* checkstop reset status */ |
| 152 | #define RSR_CSHR_SHIFT 4 |
| 153 | #define RSR_SWRS 0x00000008 /* software watchdog reset status */ |
| 154 | #define RSR_SWRS_SHIFT 3 |
| 155 | #define RSR_BMRS 0x00000004 /* bus monitop reset status */ |
| 156 | #define RSR_BMRS_SHIFT 2 |
| 157 | #define RSR_SRS 0x00000002 /* soft reset status */ |
| 158 | #define RSR_SRS_SHIFT 1 |
| 159 | #define RSR_HRS 0x00000001 /* hard reset status */ |
| 160 | #define RSR_HRS_SHIFT 0 |
| 161 | #define RSR_RES ~(RSR_SWSR | RSR_SWHR |\ |
| 162 | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ |
| 163 | RSR_BMRS | RSR_SRS | RSR_HRS) |
| 164 | /* RMR - Reset Mode Register |
| 165 | */ |
| 166 | #define RMR_CSRE 0x00000001 /* checkstop reset enable */ |
| 167 | #define RMR_CSRE_SHIFT 0 |
| 168 | #define RMR_RES ~(RMR_CSRE) |
| 169 | |
| 170 | /* RCR - Reset Control Register |
| 171 | */ |
| 172 | #define RCR_SWHR 0x00000002 /* software hard reset */ |
| 173 | #define RCR_SWSR 0x00000001 /* software soft reset */ |
| 174 | #define RCR_RES ~(RCR_SWHR | RCR_SWSR) |
| 175 | |
| 176 | /* RCER - Reset Control Enable Register |
| 177 | */ |
| 178 | #define RCER_CRE 0x00000001 /* software hard reset */ |
| 179 | #define RCER_RES ~(RCER_CRE) |
| 180 | |
| 181 | /* SPMR - System PLL Mode Register |
| 182 | */ |
| 183 | #define SPMR_SPMF 0x0F000000 |
| 184 | #define SPMR_SPMF_SHIFT 24 |
| 185 | #define SPMR_CPMF 0x000F0000 |
| 186 | #define SPMR_CPMF_SHIFT 16 |
| 187 | |
| 188 | /* SCFR1 System Clock Frequency Register 1 |
| 189 | */ |
| John Rigby | edc27dd | 2008-01-30 13:36:56 -0700 | [diff] [blame] | 190 | #define SCFR1_IPS_DIV 0x3 |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 191 | #define SCFR1_IPS_DIV_MASK 0x03800000 |
| 192 | #define SCFR1_IPS_DIV_SHIFT 23 |
| 193 | |
| John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 194 | #define SCFR1_PCI_DIV 0x6 |
| 195 | #define SCFR1_PCI_DIV_MASK 0x00700000 |
| 196 | #define SCFR1_PCI_DIV_SHIFT 20 |
| 197 | |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 198 | /* SCFR2 System Clock Frequency Register 2 |
| 199 | */ |
| 200 | #define SCFR2_SYS_DIV 0xFC000000 |
| 201 | #define SCFR2_SYS_DIV_SHIFT 26 |
| 202 | |
| 203 | /* SCCR - System Clock Control Registers |
| 204 | */ |
| 205 | |
| 206 | /* System Clock Control Register 1 commands */ |
| 207 | #define CLOCK_SCCR1_CFG_EN 0x80000000 |
| 208 | #define CLOCK_SCCR1_LPC_EN 0x40000000 |
| 209 | #define CLOCK_SCCR1_NFC_EN 0x20000000 |
| 210 | #define CLOCK_SCCR1_PATA_EN 0x10000000 |
| 211 | #define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) |
| 212 | #define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 |
| 213 | #define CLOCK_SCCR1_SATA_EN 0x00004000 |
| 214 | #define CLOCK_SCCR1_FEC_EN 0x00002000 |
| 215 | #define CLOCK_SCCR1_TPR_EN 0x00001000 |
| 216 | #define CLOCK_SCCR1_PCI_EN 0x00000800 |
| 217 | #define CLOCK_SCCR1_DDR_EN 0x00000400 |
| 218 | |
| 219 | /* System Clock Control Register 2 commands */ |
| 220 | #define CLOCK_SCCR2_DIU_EN 0x80000000 |
| 221 | #define CLOCK_SCCR2_AXE_EN 0x40000000 |
| 222 | #define CLOCK_SCCR2_MEM_EN 0x20000000 |
| 223 | #define CLOCK_SCCR2_USB2_EN 0x10000000 |
| 224 | #define CLOCK_SCCR2_USB1_EN 0x08000000 |
| 225 | #define CLOCK_SCCR2_I2C_EN 0x04000000 |
| 226 | #define CLOCK_SCCR2_BDLC_EN 0x02000000 |
| 227 | #define CLOCK_SCCR2_SDHC_EN 0x01000000 |
| 228 | #define CLOCK_SCCR2_SPDIF_EN 0x00800000 |
| 229 | #define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 |
| 230 | #define CLOCK_SCCR2_MBX_EN 0x00200000 |
| 231 | #define CLOCK_SCCR2_MBX_3D_EN 0x00100000 |
| 232 | #define CLOCK_SCCR2_IIM_EN 0x00080000 |
| 233 | |
| 234 | /* PSC FIFO Command values */ |
| 235 | #define PSC_FIFO_RESET_SLICE 0x80 |
| 236 | #define PSC_FIFO_ENABLE_SLICE 0x01 |
| 237 | |
| 238 | /* PSC FIFO Controller Command values */ |
| 239 | #define FIFOC_ENABLE_CLOCK_GATE 0x01 |
| 240 | #define FIFOC_DISABLE_CLOCK_GATE 0x00 |
| 241 | |
| 242 | /* PSC FIFO status */ |
| 243 | #define PSC_FIFO_EMPTY 0x01 |
| 244 | |
| 245 | /* PSC Command values */ |
| 246 | #define PSC_RX_ENABLE 0x01 |
| 247 | #define PSC_RX_DISABLE 0x02 |
| 248 | #define PSC_TX_ENABLE 0x04 |
| 249 | #define PSC_TX_DISABLE 0x08 |
| 250 | #define PSC_SEL_MODE_REG_1 0x10 |
| 251 | #define PSC_RST_RX 0x20 |
| 252 | #define PSC_RST_TX 0x30 |
| 253 | #define PSC_RST_ERR_STAT 0x40 |
| 254 | #define PSC_RST_BRK_CHG_INT 0x50 |
| 255 | #define PSC_START_BRK 0x60 |
| 256 | #define PSC_STOP_BRK 0x70 |
| 257 | |
| 258 | /* PSC status register bits */ |
| 259 | #define PSC_SR_CDE 0x0080 |
| 260 | #define PSC_SR_TXEMP 0x0800 |
| 261 | #define PSC_SR_OE 0x1000 |
| 262 | #define PSC_SR_PE 0x2000 |
| 263 | #define PSC_SR_FE 0x4000 |
| 264 | #define PSC_SR_RB 0x8000 |
| 265 | |
| 266 | /* PSC mode fields */ |
| 267 | #define PSC_MODE_5_BITS 0x00 |
| 268 | #define PSC_MODE_6_BITS 0x01 |
| 269 | #define PSC_MODE_7_BITS 0x02 |
| 270 | #define PSC_MODE_8_BITS 0x03 |
| 271 | #define PSC_MODE_PAREVEN 0x00 |
| 272 | #define PSC_MODE_PARODD 0x04 |
| 273 | #define PSC_MODE_PARFORCE 0x08 |
| 274 | #define PSC_MODE_PARNONE 0x10 |
| 275 | #define PSC_MODE_ENTIMEOUT 0x20 |
| 276 | #define PSC_MODE_RXRTS 0x80 |
| 277 | #define PSC_MODE_1_STOPBIT 0x07 |
| 278 | |
| 279 | /* |
| 280 | * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs |
| 281 | * |
| 282 | * NOTE: individual PSC units are free to use whatever area (and size) of the |
| 283 | * FIFOC internal memory, so make sure memory areas for FIFO slices used by |
| 284 | * different PSCs do not overlap! |
| 285 | * |
| 286 | * Overall size of FIFOC memory is not documented in the MPC5121e RM, but |
| 287 | * tests indicate that it is 1024 words total. |
| 288 | */ |
| 289 | #define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */ |
| 290 | #define FIFOC_PSC0_TX_ADDR 0x0 |
| 291 | #define FIFOC_PSC0_RX_SIZE 0x0 |
| 292 | #define FIFOC_PSC0_RX_ADDR 0x0 |
| 293 | |
| 294 | #define FIFOC_PSC1_TX_SIZE 0x0 |
| 295 | #define FIFOC_PSC1_TX_ADDR 0x0 |
| 296 | #define FIFOC_PSC1_RX_SIZE 0x0 |
| 297 | #define FIFOC_PSC1_RX_ADDR 0x0 |
| 298 | |
| 299 | #define FIFOC_PSC2_TX_SIZE 0x0 |
| 300 | #define FIFOC_PSC2_TX_ADDR 0x0 |
| 301 | #define FIFOC_PSC2_RX_SIZE 0x0 |
| 302 | #define FIFOC_PSC2_RX_ADDR 0x0 |
| 303 | |
| 304 | #define FIFOC_PSC3_TX_SIZE 0x04 |
| 305 | #define FIFOC_PSC3_TX_ADDR 0x0 |
| 306 | #define FIFOC_PSC3_RX_SIZE 0x04 |
| 307 | #define FIFOC_PSC3_RX_ADDR 0x10 |
| 308 | |
| 309 | #define FIFOC_PSC4_TX_SIZE 0x0 |
| 310 | #define FIFOC_PSC4_TX_ADDR 0x0 |
| 311 | #define FIFOC_PSC4_RX_SIZE 0x0 |
| 312 | #define FIFOC_PSC4_RX_ADDR 0x0 |
| 313 | |
| 314 | #define FIFOC_PSC5_TX_SIZE 0x0 |
| 315 | #define FIFOC_PSC5_TX_ADDR 0x0 |
| 316 | #define FIFOC_PSC5_RX_SIZE 0x0 |
| 317 | #define FIFOC_PSC5_RX_ADDR 0x0 |
| 318 | |
| 319 | #define FIFOC_PSC6_TX_SIZE 0x0 |
| 320 | #define FIFOC_PSC6_TX_ADDR 0x0 |
| 321 | #define FIFOC_PSC6_RX_SIZE 0x0 |
| 322 | #define FIFOC_PSC6_RX_ADDR 0x0 |
| 323 | |
| 324 | #define FIFOC_PSC7_TX_SIZE 0x0 |
| 325 | #define FIFOC_PSC7_TX_ADDR 0x0 |
| 326 | #define FIFOC_PSC7_RX_SIZE 0x0 |
| 327 | #define FIFOC_PSC7_RX_ADDR 0x0 |
| 328 | |
| 329 | #define FIFOC_PSC8_TX_SIZE 0x0 |
| 330 | #define FIFOC_PSC8_TX_ADDR 0x0 |
| 331 | #define FIFOC_PSC8_RX_SIZE 0x0 |
| 332 | #define FIFOC_PSC8_RX_ADDR 0x0 |
| 333 | |
| 334 | #define FIFOC_PSC9_TX_SIZE 0x0 |
| 335 | #define FIFOC_PSC9_TX_ADDR 0x0 |
| 336 | #define FIFOC_PSC9_RX_SIZE 0x0 |
| 337 | #define FIFOC_PSC9_RX_ADDR 0x0 |
| 338 | |
| 339 | #define FIFOC_PSC10_TX_SIZE 0x0 |
| 340 | #define FIFOC_PSC10_TX_ADDR 0x0 |
| 341 | #define FIFOC_PSC10_RX_SIZE 0x0 |
| 342 | #define FIFOC_PSC10_RX_ADDR 0x0 |
| 343 | |
| 344 | #define FIFOC_PSC11_TX_SIZE 0x0 |
| 345 | #define FIFOC_PSC11_TX_ADDR 0x0 |
| 346 | #define FIFOC_PSC11_RX_SIZE 0x0 |
| 347 | #define FIFOC_PSC11_RX_ADDR 0x0 |
| 348 | |
| 349 | /* IO Control Register |
| 350 | */ |
| Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 351 | #define IOCTL_MEM 0x000 |
| 352 | #define IOCTL_GP 0x004 |
| 353 | #define IOCTL_LPC_CLK 0x008 |
| 354 | #define IOCTL_LPC_OE 0x00C |
| 355 | #define IOCTL_LPC_RWB 0x010 |
| 356 | #define IOCTL_LPC_ACK 0x014 |
| 357 | #define IOCTL_LPC_CS0 0x018 |
| 358 | #define IOCTL_NFC_CE0 0x01C |
| 359 | #define IOCTL_LPC_CS1 0x020 |
| 360 | #define IOCTL_LPC_CS2 0x024 |
| 361 | #define IOCTL_LPC_AX03 0x028 |
| 362 | #define IOCTL_EMB_AX02 0x02C |
| 363 | #define IOCTL_EMB_AX01 0x030 |
| 364 | #define IOCTL_EMB_AX00 0x034 |
| 365 | #define IOCTL_EMB_AD31 0x038 |
| 366 | #define IOCTL_EMB_AD30 0x03C |
| 367 | #define IOCTL_EMB_AD29 0x040 |
| 368 | #define IOCTL_EMB_AD28 0x044 |
| 369 | #define IOCTL_EMB_AD27 0x048 |
| 370 | #define IOCTL_EMB_AD26 0x04C |
| 371 | #define IOCTL_EMB_AD25 0x050 |
| 372 | #define IOCTL_EMB_AD24 0x054 |
| 373 | #define IOCTL_EMB_AD23 0x058 |
| 374 | #define IOCTL_EMB_AD22 0x05C |
| 375 | #define IOCTL_EMB_AD21 0x060 |
| 376 | #define IOCTL_EMB_AD20 0x064 |
| 377 | #define IOCTL_EMB_AD19 0x068 |
| 378 | #define IOCTL_EMB_AD18 0x06C |
| 379 | #define IOCTL_EMB_AD17 0x070 |
| 380 | #define IOCTL_EMB_AD16 0x074 |
| 381 | #define IOCTL_EMB_AD15 0x078 |
| 382 | #define IOCTL_EMB_AD14 0x07C |
| 383 | #define IOCTL_EMB_AD13 0x080 |
| 384 | #define IOCTL_EMB_AD12 0x084 |
| 385 | #define IOCTL_EMB_AD11 0x088 |
| 386 | #define IOCTL_EMB_AD10 0x08C |
| 387 | #define IOCTL_EMB_AD09 0x090 |
| 388 | #define IOCTL_EMB_AD08 0x094 |
| 389 | #define IOCTL_EMB_AD07 0x098 |
| 390 | #define IOCTL_EMB_AD06 0x09C |
| 391 | #define IOCTL_EMB_AD05 0x0A0 |
| 392 | #define IOCTL_EMB_AD04 0x0A4 |
| 393 | #define IOCTL_EMB_AD03 0x0A8 |
| 394 | #define IOCTL_EMB_AD02 0x0AC |
| 395 | #define IOCTL_EMB_AD01 0x0B0 |
| 396 | #define IOCTL_EMB_AD00 0x0B4 |
| 397 | #define IOCTL_PATA_CE1 0x0B8 |
| 398 | #define IOCTL_PATA_CE2 0x0BC |
| 399 | #define IOCTL_PATA_ISOLATE 0x0C0 |
| 400 | #define IOCTL_PATA_IOR 0x0C4 |
| 401 | #define IOCTL_PATA_IOW 0x0C8 |
| 402 | #define IOCTL_PATA_IOCHRDY 0x0CC |
| 403 | #define IOCTL_PATA_INTRQ 0x0D0 |
| 404 | #define IOCTL_PATA_DRQ 0x0D4 |
| 405 | #define IOCTL_PATA_DACK 0x0D8 |
| 406 | #define IOCTL_NFC_WP 0x0DC |
| 407 | #define IOCTL_NFC_RB 0x0E0 |
| 408 | #define IOCTL_NFC_ALE 0x0E4 |
| 409 | #define IOCTL_NFC_CLE 0x0E8 |
| 410 | #define IOCTL_NFC_WE 0x0EC |
| 411 | #define IOCTL_NFC_RE 0x0F0 |
| 412 | #define IOCTL_PCI_AD31 0x0F4 |
| 413 | #define IOCTL_PCI_AD30 0x0F8 |
| 414 | #define IOCTL_PCI_AD29 0x0FC |
| 415 | #define IOCTL_PCI_AD28 0x100 |
| 416 | #define IOCTL_PCI_AD27 0x104 |
| 417 | #define IOCTL_PCI_AD26 0x108 |
| 418 | #define IOCTL_PCI_AD25 0x10C |
| 419 | #define IOCTL_PCI_AD24 0x110 |
| 420 | #define IOCTL_PCI_AD23 0x114 |
| 421 | #define IOCTL_PCI_AD22 0x118 |
| 422 | #define IOCTL_PCI_AD21 0x11C |
| 423 | #define IOCTL_PCI_AD20 0x120 |
| 424 | #define IOCTL_PCI_AD19 0x124 |
| 425 | #define IOCTL_PCI_AD18 0x128 |
| 426 | #define IOCTL_PCI_AD17 0x12C |
| 427 | #define IOCTL_PCI_AD16 0x130 |
| 428 | #define IOCTL_PCI_AD15 0x134 |
| 429 | #define IOCTL_PCI_AD14 0x138 |
| 430 | #define IOCTL_PCI_AD13 0x13C |
| 431 | #define IOCTL_PCI_AD12 0x140 |
| 432 | #define IOCTL_PCI_AD11 0x144 |
| 433 | #define IOCTL_PCI_AD10 0x148 |
| 434 | #define IOCTL_PCI_AD09 0x14C |
| 435 | #define IOCTL_PCI_AD08 0x150 |
| 436 | #define IOCTL_PCI_AD07 0x154 |
| 437 | #define IOCTL_PCI_AD06 0x158 |
| 438 | #define IOCTL_PCI_AD05 0x15C |
| 439 | #define IOCTL_PCI_AD04 0x160 |
| 440 | #define IOCTL_PCI_AD03 0x164 |
| 441 | #define IOCTL_PCI_AD02 0x168 |
| 442 | #define IOCTL_PCI_AD01 0x16C |
| 443 | #define IOCTL_PCI_AD00 0x170 |
| 444 | #define IOCTL_PCI_CBE0 0x174 |
| 445 | #define IOCTL_PCI_CBE1 0x178 |
| 446 | #define IOCTL_PCI_CBE2 0x17C |
| 447 | #define IOCTL_PCI_CBE3 0x180 |
| 448 | #define IOCTL_PCI_GNT2 0x184 |
| 449 | #define IOCTL_PCI_REQ2 0x188 |
| 450 | #define IOCTL_PCI_GNT1 0x18C |
| 451 | #define IOCTL_PCI_REQ1 0x190 |
| 452 | #define IOCTL_PCI_GNT0 0x194 |
| 453 | #define IOCTL_PCI_REQ0 0x198 |
| 454 | #define IOCTL_PCI_INTA 0x19C |
| 455 | #define IOCTL_PCI_CLK 0x1A0 |
| 456 | #define IOCTL_PCI_RST_OUT 0x1A4 |
| 457 | #define IOCTL_PCI_FRAME 0x1A8 |
| 458 | #define IOCTL_PCI_IDSEL 0x1AC |
| 459 | #define IOCTL_PCI_DEVSEL 0x1B0 |
| 460 | #define IOCTL_PCI_IRDY 0x1B4 |
| 461 | #define IOCTL_PCI_TRDY 0x1B8 |
| 462 | #define IOCTL_PCI_STOP 0x1BC |
| 463 | #define IOCTL_PCI_PAR 0x1C0 |
| 464 | #define IOCTL_PCI_PERR 0x1C4 |
| 465 | #define IOCTL_PCI_SERR 0x1C8 |
| 466 | #define IOCTL_SPDIF_TXCLK 0x1CC |
| 467 | #define IOCTL_SPDIF_TX 0x1D0 |
| 468 | #define IOCTL_SPDIF_RX 0x1D4 |
| 469 | #define IOCTL_I2C0_SCL 0x1D8 |
| 470 | #define IOCTL_I2C0_SDA 0x1DC |
| 471 | #define IOCTL_I2C1_SCL 0x1E0 |
| 472 | #define IOCTL_I2C1_SDA 0x1E4 |
| 473 | #define IOCTL_I2C2_SCL 0x1E8 |
| 474 | #define IOCTL_I2C2_SDA 0x1EC |
| 475 | #define IOCTL_IRQ0 0x1F0 |
| 476 | #define IOCTL_IRQ1 0x1F4 |
| 477 | #define IOCTL_CAN1_TX 0x1F8 |
| 478 | #define IOCTL_CAN2_TX 0x1FC |
| 479 | #define IOCTL_J1850_TX 0x200 |
| 480 | #define IOCTL_J1850_RX 0x204 |
| 481 | #define IOCTL_PSC_MCLK_IN 0x208 |
| 482 | #define IOCTL_PSC0_0 0x20C |
| 483 | #define IOCTL_PSC0_1 0x210 |
| 484 | #define IOCTL_PSC0_2 0x214 |
| 485 | #define IOCTL_PSC0_3 0x218 |
| 486 | #define IOCTL_PSC0_4 0x21C |
| 487 | #define IOCTL_PSC1_0 0x220 |
| 488 | #define IOCTL_PSC1_1 0x224 |
| 489 | #define IOCTL_PSC1_2 0x228 |
| 490 | #define IOCTL_PSC1_3 0x22C |
| 491 | #define IOCTL_PSC1_4 0x230 |
| 492 | #define IOCTL_PSC2_0 0x234 |
| 493 | #define IOCTL_PSC2_1 0x238 |
| 494 | #define IOCTL_PSC2_2 0x23C |
| 495 | #define IOCTL_PSC2_3 0x240 |
| 496 | #define IOCTL_PSC2_4 0x244 |
| 497 | #define IOCTL_PSC3_0 0x248 |
| 498 | #define IOCTL_PSC3_1 0x24C |
| 499 | #define IOCTL_PSC3_2 0x250 |
| 500 | #define IOCTL_PSC3_3 0x254 |
| 501 | #define IOCTL_PSC3_4 0x258 |
| 502 | #define IOCTL_PSC4_0 0x25C |
| 503 | #define IOCTL_PSC4_1 0x260 |
| 504 | #define IOCTL_PSC4_2 0x264 |
| 505 | #define IOCTL_PSC4_3 0x268 |
| 506 | #define IOCTL_PSC4_4 0x26C |
| 507 | #define IOCTL_PSC5_0 0x270 |
| 508 | #define IOCTL_PSC5_1 0x274 |
| 509 | #define IOCTL_PSC5_2 0x278 |
| 510 | #define IOCTL_PSC5_3 0x27C |
| 511 | #define IOCTL_PSC5_4 0x280 |
| 512 | #define IOCTL_PSC6_0 0x284 |
| 513 | #define IOCTL_PSC6_1 0x288 |
| 514 | #define IOCTL_PSC6_2 0x28C |
| 515 | #define IOCTL_PSC6_3 0x290 |
| 516 | #define IOCTL_PSC6_4 0x294 |
| 517 | #define IOCTL_PSC7_0 0x298 |
| 518 | #define IOCTL_PSC7_1 0x29C |
| 519 | #define IOCTL_PSC7_2 0x2A0 |
| 520 | #define IOCTL_PSC7_3 0x2A4 |
| 521 | #define IOCTL_PSC7_4 0x2A8 |
| 522 | #define IOCTL_PSC8_0 0x2AC |
| 523 | #define IOCTL_PSC8_1 0x2B0 |
| 524 | #define IOCTL_PSC8_2 0x2B4 |
| 525 | #define IOCTL_PSC8_3 0x2B8 |
| 526 | #define IOCTL_PSC8_4 0x2BC |
| 527 | #define IOCTL_PSC9_0 0x2C0 |
| 528 | #define IOCTL_PSC9_1 0x2C4 |
| 529 | #define IOCTL_PSC9_2 0x2C8 |
| 530 | #define IOCTL_PSC9_3 0x2CC |
| 531 | #define IOCTL_PSC9_4 0x2D0 |
| 532 | #define IOCTL_PSC10_0 0x2D4 |
| 533 | #define IOCTL_PSC10_1 0x2D8 |
| 534 | #define IOCTL_PSC10_2 0x2DC |
| 535 | #define IOCTL_PSC10_3 0x2E0 |
| 536 | #define IOCTL_PSC10_4 0x2E4 |
| 537 | #define IOCTL_PSC11_0 0x2E8 |
| 538 | #define IOCTL_PSC11_1 0x2EC |
| 539 | #define IOCTL_PSC11_2 0x2F0 |
| 540 | #define IOCTL_PSC11_3 0x2F4 |
| 541 | #define IOCTL_PSC11_4 0x2F8 |
| 542 | #define IOCTL_HRESET 0x2FC |
| 543 | #define IOCTL_SRESET 0x300 |
| 544 | #define IOCTL_CKSTP_OUT 0x304 |
| 545 | #define IOCTL_USB2_VBUS_PWR_FAULT 0x308 |
| 546 | #define IOCTL_USB2_VBUS_PWR_SELECT 0x30C |
| 547 | #define IOCTL_USB2_PHY_DRVV_BUS 0x310 |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 548 | |
| Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 549 | #ifndef __ASSEMBLY__ |
| 550 | |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 551 | |
| Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 552 | /* IO pin fields */ |
| 553 | #define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ |
| 554 | #define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ |
| 555 | #define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ |
| 556 | #define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ |
| 557 | #define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ |
| 558 | #define IO_PIN_DS(v) ((v)) /* slew rate */ |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 559 | |
| Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 560 | typedef struct iopin_t { |
| 561 | int p_offset; /* offset from IOCTL_MEM_OFFSET */ |
| 562 | int nr_pins; /* number of pins to set this way */ |
| 563 | int bit_or; /* or in the value instead of overwrite */ |
| 564 | u_long val; /* value to write or or */ |
| 565 | }iopin_t; |
| 566 | |
| 567 | void iopin_initialize(iopin_t *,int); |
| 568 | #endif |
| 569 | |
| 570 | /* Indexes in regs array */ |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 571 | /* Set for DDR */ |
| 572 | #define IOCTRL_MUX_DDR 0x00000036 |
| 573 | |
| 574 | /* Register Offset Base */ |
| Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 575 | #define MPC512X_FEC (CONFIG_SYS_IMMR + 0x02800) |
| Ralph Kondziella | d074bfe | 2009-01-26 12:34:36 -0700 | [diff] [blame] | 576 | #define MPC512X_PATA (CONFIG_SYS_IMMR + 0x10200) |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 577 | |
| Martha Marx | 5d3e23f | 2009-01-26 10:45:07 -0700 | [diff] [blame] | 578 | /* IIM control */ |
| 579 | #define IIM_SET_UA(bk, f) ((bk << 3) | (f >> 5)) |
| 580 | #define IIM_SET_LA(f, bit) (((f & 0x0000001f) << 3) | bit) |
| 581 | #define IIM_STAT_BUSY 0x00000080 |
| 582 | #define IIM_STAT_PRGD 0x00000002 |
| 583 | #define IIM_STAT_SNSD 0x00000001 |
| 584 | #define IIM_ERR_WPE 0x00000040 |
| 585 | #define IIM_ERR_OPE 0x00000020 |
| 586 | #define IIM_ERR_RPE 0x00000010 |
| 587 | #define IIM_ERR_WLRE 0x00000008 |
| 588 | #define IIM_ERR_SNSE 0x00000004 |
| 589 | #define IIM_ERR_PARITYE 0x00000002 |
| 590 | #define IIM_PRG_P_SET 0x000000aa |
| 591 | #define IIM_PRG_P_UNSET 0 |
| 592 | #define IIM_FCTL_PROG_PULSE 0x00000020 |
| 593 | #define IIM_FCTL_PROG 0x00000001 |
| 594 | #define IIM_FCTL_ESNS_N 0x00000008 |
| 595 | #define IIM_FBAC_FBWP 0x00000080 |
| 596 | #define IIM_FBAC_FBOP 0x00000040 |
| 597 | #define IIM_FBAC_FBRP 0x00000020 |
| 598 | #define IIM_FBAC_FBESP 0x00000008 |
| 599 | #define IIM_PROTECTION 0x000000e8 |
| 600 | #define IIM_FMAX 31 |
| 601 | |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 602 | /* Number of I2C buses */ |
| 603 | #define I2C_BUS_CNT 3 |
| 604 | |
| 605 | /* I2Cn control register bits */ |
| 606 | #define I2C_EN 0x80 |
| 607 | #define I2C_IEN 0x40 |
| 608 | #define I2C_STA 0x20 |
| 609 | #define I2C_TX 0x10 |
| 610 | #define I2C_TXAK 0x08 |
| 611 | #define I2C_RSTA 0x04 |
| 612 | #define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) |
| 613 | |
| 614 | /* I2Cn status register bits */ |
| 615 | #define I2C_CF 0x80 |
| 616 | #define I2C_AAS 0x40 |
| 617 | #define I2C_BB 0x20 |
| 618 | #define I2C_AL 0x10 |
| 619 | #define I2C_SRW 0x04 |
| 620 | #define I2C_IF 0x02 |
| 621 | #define I2C_RXAK 0x01 |
| 622 | |
| John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 623 | /* POTAR - PCI Outbound Translation Address Register |
| 624 | */ |
| 625 | #define POTAR_TA_MASK 0x000fffff |
| 626 | |
| 627 | /* POBAR - PCI Outbound Base Address Register |
| 628 | */ |
| 629 | #define POBAR_BA_MASK 0x000fffff |
| 630 | |
| 631 | /* POCMR - PCI Outbound Comparision Mask Register |
| 632 | */ |
| 633 | #define POCMR_EN 0x80000000 |
| 634 | #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ |
| 635 | #define POCMR_PRE 0x20000000 /* prefetch enable */ |
| 636 | #define POCMR_SBS 0x00100000 /* special byte swap enable */ |
| 637 | #define POCMR_CM_MASK 0x000fffff |
| 638 | #define POCMR_CM_4G 0x00000000 |
| 639 | #define POCMR_CM_2G 0x00080000 |
| 640 | #define POCMR_CM_1G 0x000C0000 |
| 641 | #define POCMR_CM_512M 0x000E0000 |
| 642 | #define POCMR_CM_256M 0x000F0000 |
| 643 | #define POCMR_CM_128M 0x000F8000 |
| 644 | #define POCMR_CM_64M 0x000FC000 |
| 645 | #define POCMR_CM_32M 0x000FE000 |
| 646 | #define POCMR_CM_16M 0x000FF000 |
| 647 | #define POCMR_CM_8M 0x000FF800 |
| 648 | #define POCMR_CM_4M 0x000FFC00 |
| 649 | #define POCMR_CM_2M 0x000FFE00 |
| 650 | #define POCMR_CM_1M 0x000FFF00 |
| 651 | #define POCMR_CM_512K 0x000FFF80 |
| 652 | #define POCMR_CM_256K 0x000FFFC0 |
| 653 | #define POCMR_CM_128K 0x000FFFE0 |
| 654 | #define POCMR_CM_64K 0x000FFFF0 |
| 655 | #define POCMR_CM_32K 0x000FFFF8 |
| 656 | #define POCMR_CM_16K 0x000FFFFC |
| 657 | #define POCMR_CM_8K 0x000FFFFE |
| 658 | #define POCMR_CM_4K 0x000FFFFF |
| 659 | |
| 660 | /* PITAR - PCI Inbound Translation Address Register |
| 661 | */ |
| 662 | #define PITAR_TA_MASK 0x000fffff |
| 663 | |
| 664 | /* PIBAR - PCI Inbound Base/Extended Address Register |
| 665 | */ |
| 666 | #define PIBAR_MASK 0xffffffff |
| 667 | #define PIEBAR_EBA_MASK 0x000fffff |
| 668 | |
| 669 | /* PIWAR - PCI Inbound Windows Attributes Register |
| 670 | */ |
| 671 | #define PIWAR_EN 0x80000000 |
| 672 | #define PIWAR_SBS 0x40000000 |
| 673 | #define PIWAR_PF 0x20000000 |
| 674 | #define PIWAR_RTT_MASK 0x000f0000 |
| 675 | #define PIWAR_RTT_NO_SNOOP 0x00040000 |
| 676 | #define PIWAR_RTT_SNOOP 0x00050000 |
| 677 | #define PIWAR_WTT_MASK 0x0000f000 |
| 678 | #define PIWAR_WTT_NO_SNOOP 0x00004000 |
| 679 | #define PIWAR_WTT_SNOOP 0x00005000 |
| 680 | #define PIWAR_IWS_MASK 0x0000003F |
| 681 | #define PIWAR_IWS_4K 0x0000000B |
| 682 | #define PIWAR_IWS_8K 0x0000000C |
| 683 | #define PIWAR_IWS_16K 0x0000000D |
| 684 | #define PIWAR_IWS_32K 0x0000000E |
| 685 | #define PIWAR_IWS_64K 0x0000000F |
| 686 | #define PIWAR_IWS_128K 0x00000010 |
| 687 | #define PIWAR_IWS_256K 0x00000011 |
| 688 | #define PIWAR_IWS_512K 0x00000012 |
| 689 | #define PIWAR_IWS_1M 0x00000013 |
| 690 | #define PIWAR_IWS_2M 0x00000014 |
| 691 | #define PIWAR_IWS_4M 0x00000015 |
| 692 | #define PIWAR_IWS_8M 0x00000016 |
| 693 | #define PIWAR_IWS_16M 0x00000017 |
| 694 | #define PIWAR_IWS_32M 0x00000018 |
| 695 | #define PIWAR_IWS_64M 0x00000019 |
| 696 | #define PIWAR_IWS_128M 0x0000001A |
| 697 | #define PIWAR_IWS_256M 0x0000001B |
| 698 | #define PIWAR_IWS_512M 0x0000001C |
| 699 | #define PIWAR_IWS_1G 0x0000001D |
| 700 | #define PIWAR_IWS_2G 0x0000001E |
| 701 | |
| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 702 | #endif /* __MPC512X_H__ */ |