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Alex89e50d92017-02-06 19:17:34 -08001
2config BITBANGMII
3 bool "Bit-banged ethernet MII management channel support"
4
5config MV88E6352_SWITCH
6 bool "Marvell 88E6352 switch support"
7
8menuconfig PHYLIB
9 bool "Ethernet PHY (physical media interface) support"
Michal Simek5647da02018-02-06 13:23:52 +010010 depends on NET
Alex89e50d92017-02-06 19:17:34 -080011 help
12 Enable Ethernet PHY (physical media interface) support.
13
14if PHYLIB
15
Joe Hershberger46b7bd12018-03-30 11:52:16 -050016config PHY_ADDR_ENABLE
17 bool "Limit phy address"
18 default y if ARCH_SUNXI
19 help
20 Select this if you want to control which phy address is used
21
22if PHY_ADDR_ENABLE
Stefan Mavrodieve3ee5f52018-02-02 15:53:38 +020023config PHY_ADDR
24 int "PHY address"
25 default 1 if ARCH_SUNXI
26 default 0
27 help
28 The address of PHY on MII bus. Usually in range of 0 to 31.
Joe Hershberger46b7bd12018-03-30 11:52:16 -050029endif
Stefan Mavrodieve3ee5f52018-02-02 15:53:38 +020030
Florian Fainelli01b4ade2017-12-09 14:59:54 -080031config B53_SWITCH
32 bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
33 help
34 Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
35 This currently supports BCM53125 and similar models.
36
37if B53_SWITCH
38
39config B53_CPU_PORT
40 int "CPU port"
41 default 8
42
43config B53_PHY_PORTS
44 hex "Bitmask of PHY ports"
45
46endif # B53_SWITCH
47
Alex89e50d92017-02-06 19:17:34 -080048config MV88E61XX_SWITCH
49 bool "Marvel MV88E61xx Ethernet switch PHY support."
50
Tim Harveyc2cc9d42017-03-17 07:29:51 -070051if MV88E61XX_SWITCH
52
53config MV88E61XX_CPU_PORT
54 int "CPU Port"
55
56config MV88E61XX_PHY_PORTS
57 hex "Bitmask of PHY Ports"
58
59config MV88E61XX_FIXED_PORTS
60 hex "Bitmask of PHYless serdes Ports"
61
62endif # MV88E61XX_SWITCH
63
Alex89e50d92017-02-06 19:17:34 -080064config PHYLIB_10G
65 bool "Generic 10G PHY support"
66
Jeremy Gebbene662c0d2018-09-18 15:49:36 -060067menuconfig PHY_AQUANTIA
Alex89e50d92017-02-06 19:17:34 -080068 bool "Aquantia Ethernet PHYs support"
Jeremy Gebbenabe3edf2018-09-18 15:49:35 -060069 select PHY_GIGE
70 select PHYLIB_10G
Alex89e50d92017-02-06 19:17:34 -080071
Jeremy Gebbene662c0d2018-09-18 15:49:36 -060072config PHY_AQUANTIA_UPLOAD_FW
73 bool "Aquantia firmware loading support"
74 default n
75 depends on PHY_AQUANTIA
76 help
77 Aquantia PHYs use firmware which can be either loaded automatically
78 from storage directly attached to the phy or loaded by the boot loader
79 via MDIO commands. The firmware is loaded from a file, specified by
80 the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options.
81
82config PHY_AQUANTIA_FW_PART
83 string "Aquantia firmware partition"
84 depends on PHY_AQUANTIA_UPLOAD_FW
85 help
86 Partition containing the firmware file.
87
88config PHY_AQUANTIA_FW_NAME
89 string "Aquantia firmware filename"
90 depends on PHY_AQUANTIA_UPLOAD_FW
91 help
92 Firmware filename.
93
Alex89e50d92017-02-06 19:17:34 -080094config PHY_ATHEROS
95 bool "Atheros Ethernet PHYs support"
96
97config PHY_BROADCOM
98 bool "Broadcom Ethernet PHYs support"
99
100config PHY_CORTINA
101 bool "Cortina Ethernet PHYs support"
102
103config PHY_DAVICOM
104 bool "Davicom Ethernet PHYs support"
105
106config PHY_ET1011C
107 bool "LSI TruePHY ET1011C support"
108
109config PHY_LXT
110 bool "LXT971 Ethernet PHY support"
111
112config PHY_MARVELL
113 bool "Marvell Ethernet PHYs support"
114
Neil Armstrong7a4c90d2017-10-18 10:02:10 +0200115config PHY_MESON_GXL
116 bool "Amlogic Meson GXL Internal PHY support"
117
Alex89e50d92017-02-06 19:17:34 -0800118config PHY_MICREL
119 bool "Micrel Ethernet PHYs support"
Philipp Tomsich00c33612017-03-26 18:50:23 +0200120 help
121 Enable support for the GbE PHYs manufactured by Micrel (now
James Byrnebc292c22019-03-06 12:48:27 +0000122 a part of Microchip). This includes drivers for the KSZ804, KSZ8031,
123 KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx
124 family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel
125 KSZ90x1 family support" is selected).
Philipp Tomsich00c33612017-03-26 18:50:23 +0200126
127if PHY_MICREL
128
129config PHY_MICREL_KSZ9021
Alexandru Gagniuc4c69ccb2017-07-07 11:37:00 -0700130 bool
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700131 select PHY_MICREL_KSZ90X1
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700132
Philipp Tomsich00c33612017-03-26 18:50:23 +0200133config PHY_MICREL_KSZ9031
Alexandru Gagniuc4c69ccb2017-07-07 11:37:00 -0700134 bool
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700135 select PHY_MICREL_KSZ90X1
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700136
137config PHY_MICREL_KSZ90X1
138 bool "Micrel KSZ90x1 family support"
139 select PHY_GIGE
140 help
141 Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If
142 enabled, the extended register read/write for KSZ90x1 PHYs
143 is supported through the 'mdio' command and any RGMII signal
144 delays configured in the device tree will be applied to the
145 PHY during initialization.
146
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700147config PHY_MICREL_KSZ8XXX
148 bool "Micrel KSZ8xxx family support"
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700149 help
James Byrnebc292c22019-03-06 12:48:27 +0000150 Enable support for the 8000 series 10/100 PHYs manufactured by Micrel
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700151 (now a part of Microchip). This includes drivers for the KSZ804,
152 KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
153
Philipp Tomsich00c33612017-03-26 18:50:23 +0200154endif # PHY_MICREL
Alex89e50d92017-02-06 19:17:34 -0800155
John Haechtenee253f92016-12-09 22:15:17 +0000156config PHY_MSCC
157 bool "Microsemi Corp Ethernet PHYs support"
158
Alex89e50d92017-02-06 19:17:34 -0800159config PHY_NATSEMI
160 bool "National Semiconductor Ethernet PHYs support"
161
162config PHY_REALTEK
163 bool "Realtek Ethernet PHYs support"
164
kevans@FreeBSD.org7c824012018-02-14 17:02:15 -0600165config RTL8211E_PINE64_GIGABIT_FIX
166 bool "Fix gigabit throughput on some Pine64+ models"
167 depends on PHY_REALTEK
168 help
169 Configure the Realtek RTL8211E found on some Pine64+ models differently to
170 fix throughput on Gigabit links, turning off all internal delays in the
171 process. The settings that this touches are not documented in the CONFREG
172 section of the RTL8211E datasheet, but come from Realtek by way of the
173 Pine64 engineering team.
174
Alex89e50d92017-02-06 19:17:34 -0800175config RTL8211X_PHY_FORCE_MASTER
176 bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
177 depends on PHY_REALTEK
178 help
179 Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
180 This can work around link stability and data corruption issues on gigabit
181 links which can occur in slave mode on certain PHYs, e.g. on the
182 RTL8211C(L).
183
184 Please note that two directly connected devices (i.e. via crossover cable)
185 will not be able to establish a link between each other if they both force
186 master mode. Multiple devices forcing master mode when connected by a
187 network switch do not pose a problem as the switch configures its affected
188 ports into slave mode.
189
190 This option only affects gigabit links. If you must establish a direct
191 connection between two devices which both force master mode, try forcing
192 the link speed to 100MBit/s.
193
194 If unsure, say N.
195
Carlo Caionecf93d022019-01-24 08:54:37 +0000196config RTL8211F_PHY_FORCE_EEE_RXC_ON
197 bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
198 depends on PHY_REALTEK
199 default n
200 help
201 The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
202 transitions to/from a lower power consumption level (Low Power Idle
203 mode) based on link utilization. When no packets are being
204 transmitted, the system goes to Low Power Idle mode to save power.
205
206 Under particular circumstances this setting can cause issues where
207 the PHY is unable to transmit or receive any packet when in LPI mode.
208 The problem is caused when the PHY is configured to stop receiving
209 the xMII clock while it is signaling LPI. For some PHYs the bit
210 configuring this behavior is set by the Linux kernel, causing the
211 issue in U-Boot on reboot if the PHY retains the register value.
212
213 Default n, which means that the PHY state is not changed. To work
214 around the issues, change this setting to y.
215
Alex89e50d92017-02-06 19:17:34 -0800216config PHY_SMSC
217 bool "Microchip(SMSC) Ethernet PHYs support"
218
219config PHY_TERANETICS
220 bool "Teranetics Ethernet PHYs support"
221
222config PHY_TI
223 bool "Texas Instruments Ethernet PHYs support"
224
225config PHY_VITESSE
226 bool "Vitesse Ethernet PHYs support"
227
228config PHY_XILINX
229 bool "Xilinx Ethernet PHYs support"
230
Hannes Schmelzerda494602017-03-23 15:11:43 +0100231config PHY_FIXED
232 bool "Fixed-Link PHY"
233 depends on DM_ETH
234 help
235 Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
236 connection (MII, RGMII, ...).
237 There is nothing like autoneogation and so
238 on, the link is always up with fixed speed and fixed duplex-setting.
239 More information: doc/device-tree-bindings/net/fixed-link.txt
240
Alex89e50d92017-02-06 19:17:34 -0800241endif #PHYLIB