| Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * QorIQ RDB boards configuration file |
| 25 | */ |
| 26 | #ifndef __CONFIG_H |
| 27 | #define __CONFIG_H |
| 28 | |
| 29 | #ifdef CONFIG_36BIT |
| 30 | #define CONFIG_PHYS_64BIT |
| 31 | #endif |
| 32 | |
| 33 | #if defined(CONFIG_P1020MBG) |
| 34 | #define CONFIG_BOARDNAME "P1020MBG" |
| 35 | #define CONFIG_P1020 |
| 36 | #define CONFIG_VSC7385_ENET |
| 37 | #define CONFIG_SLIC |
| 38 | #define __SW_BOOT_MASK 0x03 |
| 39 | #define __SW_BOOT_NOR 0xe4 |
| 40 | #define __SW_BOOT_SD 0x54 |
| 41 | #endif |
| 42 | |
| 43 | #if defined(CONFIG_P1020UTM) |
| 44 | #define CONFIG_BOARDNAME "P1020UTM" |
| 45 | #define CONFIG_P1020 |
| 46 | #define __SW_BOOT_MASK 0x03 |
| 47 | #define __SW_BOOT_NOR 0xe0 |
| 48 | #define __SW_BOOT_SD 0x50 |
| 49 | #endif |
| 50 | |
| 51 | #if defined(CONFIG_P1020RDB) |
| 52 | #define CONFIG_BOARDNAME "P1020RDB" |
| 53 | #define CONFIG_NAND_FSL_ELBC |
| 54 | #define CONFIG_P1020 |
| 55 | #define CONFIG_SPI_FLASH |
| 56 | #define CONFIG_VSC7385_ENET |
| 57 | #define CONFIG_SLIC |
| 58 | #define __SW_BOOT_MASK 0x03 |
| 59 | #define __SW_BOOT_NOR 0x5c |
| 60 | #define __SW_BOOT_SPI 0x1c |
| 61 | #define __SW_BOOT_SD 0x9c |
| 62 | #define __SW_BOOT_NAND 0xec |
| 63 | #define __SW_BOOT_PCIE 0x6c |
| 64 | #endif |
| 65 | |
| 66 | #if defined(CONFIG_P1021RDB) |
| 67 | #define CONFIG_BOARDNAME "P1021RDB" |
| 68 | #define CONFIG_NAND_FSL_ELBC |
| 69 | #define CONFIG_P1021 |
| 70 | #define CONFIG_QE |
| 71 | #define CONFIG_SPI_FLASH |
| 72 | #define CONFIG_VSC7385_ENET |
| 73 | #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of |
| 74 | addresses in the LBC */ |
| 75 | #define __SW_BOOT_MASK 0x03 |
| 76 | #define __SW_BOOT_NOR 0x5c |
| 77 | #define __SW_BOOT_SPI 0x1c |
| 78 | #define __SW_BOOT_SD 0x9c |
| 79 | #define __SW_BOOT_NAND 0xec |
| 80 | #define __SW_BOOT_PCIE 0x6c |
| 81 | #endif |
| 82 | |
| 83 | #if defined(CONFIG_P1024RDB) |
| 84 | #define CONFIG_BOARDNAME "P1024RDB" |
| 85 | #define CONFIG_NAND_FSL_ELBC |
| 86 | #define CONFIG_P1024 |
| 87 | #define CONFIG_SLIC |
| 88 | #define CONFIG_SPI_FLASH |
| 89 | #define __SW_BOOT_MASK 0xf3 |
| 90 | #define __SW_BOOT_NOR 0x00 |
| 91 | #define __SW_BOOT_SPI 0x08 |
| 92 | #define __SW_BOOT_SD 0x04 |
| 93 | #define __SW_BOOT_NAND 0x0c |
| 94 | #endif |
| 95 | |
| 96 | #if defined(CONFIG_P1025RDB) |
| 97 | #define CONFIG_BOARDNAME "P1025RDB" |
| 98 | #define CONFIG_NAND_FSL_ELBC |
| 99 | #define CONFIG_P1025 |
| 100 | #define CONFIG_QE |
| 101 | #define CONFIG_SLIC |
| 102 | #define CONFIG_SPI_FLASH |
| 103 | |
| 104 | #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of |
| 105 | addresses in the LBC */ |
| 106 | #define __SW_BOOT_MASK 0xf3 |
| 107 | #define __SW_BOOT_NOR 0x00 |
| 108 | #define __SW_BOOT_SPI 0x08 |
| 109 | #define __SW_BOOT_SD 0x04 |
| 110 | #define __SW_BOOT_NAND 0x0c |
| 111 | #endif |
| 112 | |
| 113 | #if defined(CONFIG_P2020RDB) |
| 114 | #define CONFIG_BOARDNAME "P2020RDB" |
| 115 | #define CONFIG_NAND_FSL_ELBC |
| 116 | #define CONFIG_P2020 |
| 117 | #define CONFIG_SPI_FLASH |
| 118 | #define CONFIG_VSC7385_ENET |
| 119 | #define __SW_BOOT_MASK 0x03 |
| 120 | #define __SW_BOOT_NOR 0xc8 |
| 121 | #define __SW_BOOT_SPI 0x28 |
| 122 | #define __SW_BOOT_SD 0x68 /* or 0x18 */ |
| 123 | #define __SW_BOOT_NAND 0xe8 |
| 124 | #define __SW_BOOT_PCIE 0xa8 |
| 125 | #endif |
| 126 | |
| 127 | #ifdef CONFIG_SDCARD |
| 128 | #define CONFIG_RAMBOOT_SDCARD |
| 129 | #define CONFIG_SYS_RAMBOOT |
| 130 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 131 | #define CONFIG_SYS_TEXT_BASE 0x11000000 |
| 132 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc |
| 133 | #endif |
| 134 | |
| 135 | #ifdef CONFIG_SPIFLASH |
| 136 | #define CONFIG_RAMBOOT_SPIFLASH |
| 137 | #define CONFIG_SYS_RAMBOOT |
| 138 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 139 | #define CONFIG_SYS_TEXT_BASE 0x11000000 |
| 140 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc |
| 141 | #endif |
| 142 | |
| 143 | #if defined(CONFIG_NAND) && defined(CONFIG_NAND_FSL_ELBC) |
| 144 | #define CONFIG_NAND_U_BOOT |
| 145 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 146 | #define CONFIG_SYS_RAMBOOT |
| 147 | #define CONFIG_SYS_TEXT_BASE_SPL 0xff800000 |
| 148 | #ifdef CONFIG_NAND_SPL |
| 149 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL |
| 150 | #else |
| 151 | #define CONFIG_SYS_TEXT_BASE 0x11001000 |
| 152 | #endif /* CONFIG_NAND_SPL */ |
| 153 | #endif |
| 154 | |
| 155 | #ifndef CONFIG_SYS_TEXT_BASE |
| 156 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 |
| 157 | #endif |
| 158 | |
| 159 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 160 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 161 | #endif |
| 162 | |
| 163 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 164 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 165 | #endif |
| 166 | |
| 167 | /* High Level Configuration Options */ |
| 168 | #define CONFIG_BOOKE |
| 169 | #define CONFIG_E500 |
| 170 | #define CONFIG_MPC85xx |
| 171 | |
| 172 | #define CONFIG_MP |
| 173 | |
| 174 | #define CONFIG_FSL_ELBC |
| 175 | #define CONFIG_PCI |
| 176 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ |
| 177 | #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ |
| 178 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| 179 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ |
| 180 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| 181 | |
| 182 | #define CONFIG_FSL_LAW |
| 183 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 184 | #define CONFIG_ENV_OVERWRITE |
| 185 | |
| 186 | #define CONFIG_CMD_SATA |
| 187 | #define CONFIG_SATA_SIL3114 |
| 188 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
| 189 | #define CONFIG_LIBATA |
| 190 | #define CONFIG_LBA48 |
| 191 | |
| 192 | #if defined(CONFIG_P2020RDB) |
| 193 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 194 | #else |
| 195 | #define CONFIG_SYS_CLK_FREQ 66666666 |
| 196 | #endif |
| 197 | #define CONFIG_DDR_CLK_FREQ 66666666 |
| 198 | |
| 199 | #define CONFIG_HWCONFIG |
| 200 | /* |
| 201 | * These can be toggled for performance analysis, otherwise use default. |
| 202 | */ |
| 203 | #define CONFIG_L2_CACHE |
| 204 | #define CONFIG_BTB |
| 205 | |
| 206 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ |
| 207 | #ifdef CONFIG_PHYS_64BIT |
| 208 | #define CONFIG_ENABLE_36BIT_PHYS |
| 209 | #endif |
| 210 | |
| 211 | #ifdef CONFIG_PHYS_64BIT |
| 212 | #define CONFIG_ADDR_MAP 1 |
| 213 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
| 214 | #endif |
| 215 | |
| 216 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 217 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff |
| 218 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 219 | |
| 220 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| 221 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
| 222 | |
| 223 | /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k |
| 224 | SPL code*/ |
| 225 | #if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL) |
| 226 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| 227 | #endif |
| 228 | |
| 229 | /* DDR Setup */ |
| 230 | #define CONFIG_FSL_DDR3 |
| 231 | #define CONFIG_DDR_RAW_TIMING |
| 232 | #define CONFIG_DDR_SPD |
| 233 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
| 234 | #define SPD_EEPROM_ADDRESS 0x52 |
| 235 | #define CONFIG_FSL_DDR_INTERACTIVE |
| 236 | |
| 237 | #ifdef CONFIG_P1020MBG |
| 238 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G |
| 239 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 240 | #else |
| 241 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G |
| 242 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 |
| 243 | #endif |
| 244 | #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) |
| 245 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 246 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 247 | |
| 248 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 249 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 250 | |
| 251 | /* Default settings for DDR3 */ |
| 252 | #ifdef CONFIG_P2020RDB |
| 253 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f |
| 254 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
| 255 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 |
| 256 | #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 |
| 257 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 |
| 258 | #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 |
| 259 | |
| 260 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 261 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 |
| 262 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 |
| 263 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 |
| 264 | |
| 265 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 |
| 266 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8645F607 |
| 267 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 |
| 268 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 |
| 269 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 |
| 270 | #define CONFIG_SYS_DDR_CONTROL 0xC7000000 /* Type = DDR3 */ |
| 271 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 |
| 272 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 |
| 273 | #define CONFIG_SYS_DDR_TIMING_5 0x02401400 |
| 274 | |
| 275 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 |
| 276 | #define CONFIG_SYS_DDR_TIMING_0 0x00330104 |
| 277 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4644 |
| 278 | #define CONFIG_SYS_DDR_TIMING_2 0x0FA88CCF |
| 279 | #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 |
| 280 | #define CONFIG_SYS_DDR_MODE_1 0x00421422 |
| 281 | #define CONFIG_SYS_DDR_MODE_2 0x04000000 |
| 282 | #define CONFIG_SYS_DDR_INTERVAL 0x0C300100 |
| 283 | |
| 284 | #else |
| 285 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f |
| 286 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 |
| 287 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 |
| 288 | #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f |
| 289 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 |
| 290 | #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 |
| 291 | |
| 292 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 293 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 |
| 294 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 |
| 295 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 |
| 296 | |
| 297 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 |
| 298 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 |
| 299 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 |
| 300 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 |
| 301 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 |
| 302 | #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ |
| 303 | #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 |
| 304 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 |
| 305 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 |
| 306 | |
| 307 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 |
| 308 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 |
| 309 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 |
| 310 | #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF |
| 311 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 |
| 312 | #define CONFIG_SYS_DDR_MODE_1 0x40461520 |
| 313 | #define CONFIG_SYS_DDR_MODE_2 0x8000c000 |
| 314 | #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 |
| 315 | #endif |
| 316 | |
| 317 | #undef CONFIG_CLOCKS_IN_MHZ |
| 318 | |
| 319 | /* |
| 320 | * Memory map |
| 321 | * |
| 322 | * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable |
| 323 | * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) |
| 324 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable |
| 325 | * |
| 326 | * Localbus cacheable (TBD) |
| 327 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
| 328 | * |
| 329 | * Localbus non-cacheable |
| 330 | * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable |
| 331 | * 0xff80_0000 0xff8f_ffff NAND flash 1M non-cacheable |
| 332 | * 0xff90_0000 0xff97_ffff L2 SDRAM(REV.) 512K cacheable(optional) |
| 333 | * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable |
| 334 | * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable |
| 335 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
| 336 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| 337 | */ |
| 338 | |
| 339 | |
| 340 | /* |
| 341 | * Local Bus Definitions |
| 342 | */ |
| 343 | #if defined(CONFIG_P1020MBG) |
| 344 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ |
| 345 | #define CONFIG_SYS_FLASH_BASE 0xec000000 |
| 346 | #elif defined(CONFIG_P1020UTM) |
| 347 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ |
| 348 | #define CONFIG_SYS_FLASH_BASE 0xee000000 |
| 349 | #else |
| 350 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ |
| 351 | #define CONFIG_SYS_FLASH_BASE 0xef000000 |
| 352 | #endif |
| 353 | |
| 354 | |
| 355 | #ifdef CONFIG_PHYS_64BIT |
| 356 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
| 357 | #else |
| 358 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 359 | #endif |
| 360 | |
| 361 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ |
| 362 | | BR_PS_16 | BR_V) |
| 363 | |
| 364 | #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 |
| 365 | |
| 366 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| 367 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 368 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 369 | |
| 370 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 371 | |
| 372 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 373 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 374 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 375 | |
| 376 | #define CONFIG_FLASH_CFI_DRIVER |
| 377 | #define CONFIG_SYS_FLASH_CFI |
| 378 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 379 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 380 | |
| 381 | /* Nand Flash */ |
| 382 | #ifdef CONFIG_NAND_FSL_ELBC |
| 383 | #define CONFIG_SYS_NAND_BASE 0xff800000 |
| 384 | #ifdef CONFIG_PHYS_64BIT |
| 385 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull |
| 386 | #else |
| 387 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 388 | #endif |
| 389 | |
| 390 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 391 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 392 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 393 | #define CONFIG_CMD_NAND |
| 394 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) |
| 395 | |
| 396 | /* NAND boot: 4K NAND loader config */ |
| 397 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 |
| 398 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE) |
| 399 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) |
| 400 | #define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 |
| 401 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) |
| 402 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 |
| 403 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) |
| 404 | |
| 405 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS)) \ |
| 406 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 407 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 408 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 409 | | BR_V) /* valid */ |
| 410 | #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ |
| 411 | | OR_FCM_CSCT \ |
| 412 | | OR_FCM_CST \ |
| 413 | | OR_FCM_CHT \ |
| 414 | | OR_FCM_SCY_1 \ |
| 415 | | OR_FCM_TRLX \ |
| 416 | | OR_FCM_EHTR) |
| 417 | #endif /* CONFIG_NAND_FSL_ELBC */ |
| 418 | |
| 419 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
| 420 | |
| 421 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 422 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ |
| 423 | #ifdef CONFIG_PHYS_64BIT |
| 424 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
| 425 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR |
| 426 | /* The assembler doesn't like typecast */ |
| 427 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
| 428 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ |
| 429 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
| 430 | #else |
| 431 | /* Initial L1 address */ |
| 432 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR |
| 433 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 |
| 434 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS |
| 435 | #endif |
| 436 | /* Size of used area in RAM */ |
| 437 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
| 438 | |
| 439 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 440 | GENERATED_GBL_DATA_SIZE) |
| 441 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 442 | |
| 443 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ |
| 444 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ |
| 445 | |
| 446 | #define CONFIG_SYS_CPLD_BASE 0xffa00000 |
| 447 | #ifdef CONFIG_PHYS_64BIT |
| 448 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull |
| 449 | #else |
| 450 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE |
| 451 | #endif |
| 452 | /* CPLD config size: 1Mb */ |
| 453 | #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ |
| 454 | BR_PS_8 | BR_V) |
| 455 | #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) |
| 456 | |
| 457 | #define CONFIG_SYS_PMC_BASE 0xff980000 |
| 458 | #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE |
| 459 | #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ |
| 460 | BR_PS_8 | BR_V) |
| 461 | #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ |
| 462 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ |
| 463 | OR_GPCM_EAD) |
| 464 | |
| 465 | #ifdef CONFIG_NAND_U_BOOT |
| 466 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ |
| 467 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| 468 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 469 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
| 470 | #else |
| 471 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 472 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
| 473 | #ifdef CONFIG_NAND_FSL_ELBC |
| 474 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ |
| 475 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| 476 | #endif |
| 477 | #endif |
| 478 | #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ |
| 479 | #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ |
| 480 | |
| 481 | |
| 482 | /* Vsc7385 switch */ |
| 483 | #ifdef CONFIG_VSC7385_ENET |
| 484 | #define CONFIG_SYS_VSC7385_BASE 0xffb00000 |
| 485 | |
| 486 | #ifdef CONFIG_PHYS_64BIT |
| 487 | #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull |
| 488 | #else |
| 489 | #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE |
| 490 | #endif |
| 491 | |
| 492 | #define CONFIG_SYS_VSC7385_BR_PRELIM \ |
| 493 | (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) |
| 494 | #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ |
| 495 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ |
| 496 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
| 497 | |
| 498 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM |
| 499 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM |
| 500 | |
| 501 | /* The size of the VSC7385 firmware image */ |
| 502 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 |
| 503 | #endif |
| 504 | |
| 505 | /* Serial Port - controlled on board with jumper J8 |
| 506 | * open - index 2 |
| 507 | * shorted - index 1 |
| 508 | */ |
| 509 | #define CONFIG_CONS_INDEX 1 |
| 510 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 511 | #define CONFIG_SYS_NS16550 |
| 512 | #define CONFIG_SYS_NS16550_SERIAL |
| 513 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 514 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| 515 | #ifdef CONFIG_NAND_SPL |
| 516 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 517 | #endif |
| 518 | |
| 519 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 520 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 521 | |
| 522 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 523 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| 524 | |
| 525 | /* Use the HUSH parser */ |
| 526 | #define CONFIG_SYS_HUSH_PARSER |
| 527 | #ifdef CONFIG_SYS_HUSH_PARSER |
| 528 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 529 | #endif |
| 530 | |
| 531 | /* |
| 532 | * Pass open firmware flat tree |
| 533 | */ |
| 534 | #define CONFIG_OF_LIBFDT |
| 535 | #define CONFIG_OF_BOARD_SETUP |
| 536 | #define CONFIG_OF_STDOUT_VIA_ALIAS |
| 537 | |
| 538 | #define CONFIG_SYS_64BIT_VSPRINTF |
| 539 | #define CONFIG_SYS_64BIT_STRTOUL |
| 540 | |
| 541 | /* new uImage format support */ |
| 542 | #define CONFIG_FIT |
| 543 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
| 544 | |
| 545 | /* I2C */ |
| 546 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 547 | #define CONFIG_HARD_I2C /* I2C with hardware support */ |
| 548 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 549 | #define CONFIG_I2C_MULTI_BUS |
| 550 | #define CONFIG_I2C_CMD_TREE |
| 551 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */ |
| 552 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
| 553 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 554 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */ |
| 555 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
| 556 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 |
| 557 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ |
| 558 | |
| 559 | /* |
| 560 | * I2C2 EEPROM |
| 561 | */ |
| 562 | #undef CONFIG_ID_EEPROM |
| 563 | |
| 564 | #define CONFIG_RTC_PT7C4338 |
| 565 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 566 | #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 |
| 567 | |
| 568 | /* enable read and write access to EEPROM */ |
| 569 | #define CONFIG_CMD_EEPROM |
| 570 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
| 571 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 572 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 573 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
| 574 | |
| 575 | /* |
| 576 | * eSPI - Enhanced SPI |
| 577 | */ |
| 578 | #define CONFIG_HARD_SPI |
| 579 | #define CONFIG_FSL_ESPI |
| 580 | |
| 581 | #if defined(CONFIG_SPI_FLASH) |
| 582 | #define CONFIG_SPI_FLASH_SPANSION |
| 583 | #define CONFIG_CMD_SF |
| 584 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 585 | #define CONFIG_SF_DEFAULT_MODE 0 |
| 586 | #endif |
| 587 | |
| 588 | #if defined(CONFIG_PCI) |
| 589 | /* |
| 590 | * General PCI |
| 591 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 592 | */ |
| 593 | |
| 594 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ |
| 595 | #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" |
| 596 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 597 | #ifdef CONFIG_PHYS_64BIT |
| 598 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 |
| 599 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| 600 | #else |
| 601 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| 602 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
| 603 | #endif |
| 604 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| 605 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| 606 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 607 | #ifdef CONFIG_PHYS_64BIT |
| 608 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
| 609 | #else |
| 610 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| 611 | #endif |
| 612 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 613 | |
| 614 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ |
| 615 | #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" |
| 616 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 617 | #ifdef CONFIG_PHYS_64BIT |
| 618 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
| 619 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 620 | #else |
| 621 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
| 622 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 |
| 623 | #endif |
| 624 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 625 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 |
| 626 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 627 | #ifdef CONFIG_PHYS_64BIT |
| 628 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull |
| 629 | #else |
| 630 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 |
| 631 | #endif |
| 632 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 633 | |
| 634 | |
| 635 | /*PCIE video card used*/ |
| 636 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
| 637 | |
| 638 | /* video */ |
| 639 | #define CONFIG_VIDEO |
| 640 | #ifdef CONFIG_VIDEO |
| 641 | #define CONFIG_BIOSEMU |
| 642 | #define CONFIG_CFB_CONSOLE |
| 643 | #define CONFIG_VIDEO_SW_CURSOR |
| 644 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| 645 | #define CONFIG_ATI_RADEON_FB |
| 646 | #define CONFIG_VIDEO_LOGO |
| 647 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| 648 | #endif |
| 649 | |
| 650 | #define CONFIG_NET_MULTI |
| 651 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 652 | #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ |
| 653 | #define CONFIG_CMD_PCI |
| 654 | #define CONFIG_CMD_NET |
| 655 | |
| 656 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 657 | #define CONFIG_DOS_PARTITION |
| 658 | #endif /* CONFIG_PCI */ |
| 659 | |
| 660 | #if defined(CONFIG_TSEC_ENET) |
| 661 | |
| 662 | #ifndef CONFIG_NET_MULTI |
| 663 | #define CONFIG_NET_MULTI |
| 664 | #endif |
| 665 | |
| 666 | #define CONFIG_MII /* MII PHY management */ |
| 667 | #define CONFIG_TSEC1 |
| 668 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 669 | #define CONFIG_TSEC2 |
| 670 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| 671 | #define CONFIG_TSEC3 |
| 672 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 673 | |
| 674 | #define TSEC1_PHY_ADDR 2 |
| 675 | #define TSEC2_PHY_ADDR 0 |
| 676 | #define TSEC3_PHY_ADDR 1 |
| 677 | |
| 678 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 679 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 680 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 681 | |
| 682 | #define TSEC1_PHYIDX 0 |
| 683 | #define TSEC2_PHYIDX 0 |
| 684 | #define TSEC3_PHYIDX 0 |
| 685 | |
| 686 | #define CONFIG_ETHPRIME "eTSEC1" |
| 687 | |
| 688 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| 689 | |
| 690 | #define CONFIG_HAS_ETH0 |
| 691 | #define CONFIG_HAS_ETH1 |
| 692 | #define CONFIG_HAS_ETH2 |
| 693 | #endif /* CONFIG_TSEC_ENET */ |
| 694 | |
| 695 | #ifdef CONFIG_QE |
| 696 | /* QE microcode/firmware address */ |
| 697 | #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 |
| 698 | #define CONFIG_SYS_QE_FW_LENGTH 0x10000 |
| 699 | #endif /* CONFIG_QE */ |
| 700 | |
| 701 | #ifdef CONFIG_P1025RDB |
| 702 | /* |
| 703 | * QE UEC ethernet configuration |
| 704 | */ |
| 705 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) |
| 706 | |
| 707 | #undef CONFIG_UEC_ETH |
| 708 | #define CONFIG_PHY_MODE_NEED_CHANGE |
| 709 | |
| 710 | #define CONFIG_UEC_ETH1 /* ETH1 */ |
| 711 | #define CONFIG_HAS_ETH0 |
| 712 | |
| 713 | #ifdef CONFIG_UEC_ETH1 |
| 714 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
| 715 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ |
| 716 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ |
| 717 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH |
| 718 | #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ |
| 719 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
| 720 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
| 721 | #endif /* CONFIG_UEC_ETH1 */ |
| 722 | |
| 723 | #define CONFIG_UEC_ETH5 /* ETH5 */ |
| 724 | #define CONFIG_HAS_ETH1 |
| 725 | |
| 726 | #ifdef CONFIG_UEC_ETH5 |
| 727 | #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ |
| 728 | #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE |
| 729 | #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ |
| 730 | #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH |
| 731 | #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ |
| 732 | #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
| 733 | #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 |
| 734 | #endif /* CONFIG_UEC_ETH5 */ |
| 735 | #endif /* CONFIG_P1025RDB */ |
| 736 | |
| 737 | /* |
| 738 | * Environment |
| 739 | */ |
| 740 | #ifdef CONFIG_SYS_RAMBOOT |
| 741 | #ifdef CONFIG_RAMBOOT_SPIFLASH |
| 742 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 743 | #define CONFIG_ENV_SPI_BUS 0 |
| 744 | #define CONFIG_ENV_SPI_CS 0 |
| 745 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 |
| 746 | #define CONFIG_ENV_SPI_MODE 0 |
| 747 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 748 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
| 749 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 750 | #elif defined(CONFIG_RAMBOOT_SDCARD) |
| 751 | #define CONFIG_ENV_IS_IN_MMC |
| 752 | #define CONFIG_ENV_SIZE 0x2000 |
| 753 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 754 | #elif defined(CONFIG_NAND_U_BOOT) |
| 755 | #define CONFIG_ENV_IS_IN_NAND |
| 756 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| 757 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) |
| 758 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) |
| 759 | #else |
| 760 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
| 761 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 762 | #define CONFIG_ENV_SIZE 0x2000 |
| 763 | #endif |
| 764 | #else |
| 765 | #define CONFIG_ENV_IS_IN_FLASH |
| 766 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
| 767 | #define CONFIG_ENV_ADDR 0xfff80000 |
| 768 | #else |
| 769 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 770 | #endif |
| 771 | #define CONFIG_ENV_SIZE 0x2000 |
| 772 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
| 773 | #endif |
| 774 | |
| 775 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
| 776 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
| 777 | |
| 778 | /* |
| 779 | * Command line configuration. |
| 780 | */ |
| 781 | #include <config_cmd_default.h> |
| 782 | |
| 783 | #define CONFIG_CMD_IRQ |
| 784 | #define CONFIG_CMD_PING |
| 785 | #define CONFIG_CMD_I2C |
| 786 | #define CONFIG_CMD_MII |
| 787 | #define CONFIG_CMD_DATE |
| 788 | #define CONFIG_CMD_ELF |
| 789 | #define CONFIG_CMD_SETEXPR |
| 790 | #define CONFIG_CMD_REGINFO |
| 791 | |
| 792 | /* |
| 793 | * USB |
| 794 | */ |
| 795 | #define CONFIG_HAS_FSL_DR_USB |
| 796 | |
| 797 | #if defined(CONFIG_HAS_FSL_DR_USB) |
| 798 | #define CONFIG_USB_EHCI |
| 799 | |
| 800 | #ifdef CONFIG_USB_EHCI |
| 801 | #define CONFIG_CMD_USB |
| 802 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 803 | #define CONFIG_USB_EHCI_FSL |
| 804 | #define CONFIG_USB_STORAGE |
| 805 | #endif |
| 806 | #endif |
| 807 | |
| 808 | #define CONFIG_MMC |
| 809 | |
| 810 | #ifdef CONFIG_MMC |
| 811 | #define CONFIG_FSL_ESDHC |
| 812 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 813 | #define CONFIG_CMD_MMC |
| 814 | #define CONFIG_GENERIC_MMC |
| 815 | #endif |
| 816 | |
| 817 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ |
| 818 | || defined(CONFIG_FSL_SATA) |
| 819 | #define CONFIG_CMD_EXT2 |
| 820 | #define CONFIG_CMD_FAT |
| 821 | #define CONFIG_DOS_PARTITION |
| 822 | #endif |
| 823 | |
| 824 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 825 | |
| 826 | /* |
| 827 | * Miscellaneous configurable options |
| 828 | */ |
| 829 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 830 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 831 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 832 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
| 833 | #if defined(CONFIG_CMD_KGDB) |
| 834 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 835 | #else |
| 836 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 837 | #endif |
| 838 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 839 | /* Print Buffer Size */ |
| 840 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 841 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ |
| 842 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ |
| 843 | |
| 844 | /* |
| 845 | * For booting Linux, the board info and command line data |
| 846 | * have to be in the first 64 MB of memory, since this is |
| 847 | * the maximum mapped by the Linux kernel during initialization. |
| 848 | */ |
| 849 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ |
| 850 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 851 | |
| 852 | #if defined(CONFIG_CMD_KGDB) |
| 853 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 854 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 855 | #endif |
| 856 | |
| 857 | /* |
| 858 | * Environment Configuration |
| 859 | */ |
| 860 | #define CONFIG_HOSTNAME unknown |
| 861 | #define CONFIG_ROOTPATH /opt/nfsroot |
| 862 | #define CONFIG_BOOTFILE uImage |
| 863 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| 864 | |
| 865 | /* default location for tftp and bootm */ |
| 866 | #define CONFIG_LOADADDR 1000000 |
| 867 | |
| 868 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
| 869 | #define CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 870 | |
| 871 | #define CONFIG_BAUDRATE 115200 |
| 872 | |
| 873 | #ifdef __SW_BOOT_NOR |
| 874 | #define __NOR_RST_CMD \ |
| 875 | norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ |
| 876 | i2c mw 18 3 __SW_BOOT_MASK 1; reset |
| 877 | #endif |
| 878 | #ifdef __SW_BOOT_SPI |
| 879 | #define __SPI_RST_CMD \ |
| 880 | spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ |
| 881 | i2c mw 18 3 __SW_BOOT_MASK 1; reset |
| 882 | #endif |
| 883 | #ifdef __SW_BOOT_SD |
| 884 | #define __SD_RST_CMD \ |
| 885 | sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ |
| 886 | i2c mw 18 3 __SW_BOOT_MASK 1; reset |
| 887 | #endif |
| 888 | #ifdef __SW_BOOT_NAND |
| 889 | #define __NAND_RST_CMD \ |
| 890 | nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ |
| 891 | i2c mw 18 3 __SW_BOOT_MASK 1; reset |
| 892 | #endif |
| 893 | #ifdef __SW_BOOT_PCIE |
| 894 | #define __PCIE_RST_CMD \ |
| 895 | pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ |
| 896 | i2c mw 18 3 __SW_BOOT_MASK 1; reset |
| 897 | #endif |
| 898 | |
| 899 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 900 | "netdev=eth0\0" \ |
| 901 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ |
| 902 | "loadaddr=1000000\0" \ |
| 903 | "bootfile=uImage\0" \ |
| 904 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 905 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 906 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 907 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ |
| 908 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 909 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ |
| 910 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ |
| 911 | "consoledev=ttyS0\0" \ |
| 912 | "ramdiskaddr=2000000\0" \ |
| 913 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ |
| 914 | "fdtaddr=c00000\0" \ |
| 915 | "bdev=sda1\0" \ |
| 916 | "jffs2nor=mtdblock3\0" \ |
| 917 | "norbootaddr=ef080000\0" \ |
| 918 | "norfdtaddr=ef040000\0" \ |
| 919 | "jffs2nand=mtdblock9\0" \ |
| 920 | "nandbootaddr=100000\0" \ |
| 921 | "nandfdtaddr=80000\0" \ |
| 922 | "ramdisk_size=120000\0" \ |
| 923 | "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ |
| 924 | "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ |
| 925 | MK_STR(__NOR_RST_CMD)"\0" \ |
| 926 | MK_STR(__SPI_RST_CMD)"\0" \ |
| 927 | MK_STR(__SD_RST_CMD)"\0" \ |
| 928 | MK_STR(__NAND_RST_CMD)"\0" \ |
| 929 | MK_STR(__PCIE_RST_CMD)"\0" |
| 930 | |
| 931 | #define CONFIG_NFSBOOTCOMMAND \ |
| 932 | "setenv bootargs root=/dev/nfs rw " \ |
| 933 | "nfsroot=$serverip:$rootpath " \ |
| 934 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 935 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 936 | "tftp $loadaddr $bootfile;" \ |
| 937 | "tftp $fdtaddr $fdtfile;" \ |
| 938 | "bootm $loadaddr - $fdtaddr" |
| 939 | |
| 940 | #define CONFIG_HDBOOT \ |
| 941 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ |
| 942 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 943 | "usb start;" \ |
| 944 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ |
| 945 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ |
| 946 | "bootm $loadaddr - $fdtaddr" |
| 947 | |
| 948 | #define CONFIG_USB_FAT_BOOT \ |
| 949 | "setenv bootargs root=/dev/ram rw " \ |
| 950 | "console=$consoledev,$baudrate $othbootargs " \ |
| 951 | "ramdisk_size=$ramdisk_size;" \ |
| 952 | "usb start;" \ |
| 953 | "fatload usb 0:2 $loadaddr $bootfile;" \ |
| 954 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ |
| 955 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ |
| 956 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 957 | |
| 958 | #define CONFIG_USB_EXT2_BOOT \ |
| 959 | "setenv bootargs root=/dev/ram rw " \ |
| 960 | "console=$consoledev,$baudrate $othbootargs " \ |
| 961 | "ramdisk_size=$ramdisk_size;" \ |
| 962 | "usb start;" \ |
| 963 | "ext2load usb 0:4 $loadaddr $bootfile;" \ |
| 964 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ |
| 965 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ |
| 966 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 967 | |
| 968 | #define CONFIG_NORBOOT \ |
| 969 | "setenv bootargs root=/dev/$jffs2nor rw " \ |
| 970 | "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ |
| 971 | "bootm $norbootaddr - $norfdtaddr" |
| 972 | |
| 973 | #define CONFIG_RAMBOOTCOMMAND \ |
| 974 | "setenv bootargs root=/dev/ram rw " \ |
| 975 | "console=$consoledev,$baudrate $othbootargs " \ |
| 976 | "ramdisk_size=$ramdisk_size;" \ |
| 977 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 978 | "tftp $loadaddr $bootfile;" \ |
| 979 | "tftp $fdtaddr $fdtfile;" \ |
| 980 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 981 | |
| 982 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT |
| 983 | |
| 984 | #endif /* __CONFIG_H */ |