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git01.mediatek.com / filogic / uboot / ca8a37a4f6d7112a22c9f14cb502fdbc79d60aee / . / include / configs / hsdk.h
blob: 3684f4d6d63e2b88d73bddc70f87ea2a5006d557 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]2/*
3 * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]4 */
5
6#ifndef _CONFIG_HSDK_H_
7#define _CONFIG_HSDK_H_
8
9#include <linux/sizes.h>
10
11/*
12 * CPU configuration
13 */
Eugeniy Paltsev24e026e2018-03-26 15:57:37 +0300[diff] [blame]14#define NR_CPUS 4
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]15#define ARC_PERIPHERAL_BASE 0xF0000000
16#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
17#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
18
19/*
20 * Memory configuration
21 */
22#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
23
24#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
25#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
26#define CONFIG_SYS_SDRAM_SIZE SZ_1G
27
28#define CONFIG_SYS_INIT_SP_ADDR \
29 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
30
31#define CONFIG_SYS_MALLOC_LEN SZ_2M
Alexey Brodkin75429682018-01-19 16:13:51 +0300[diff] [blame]32#define CONFIG_SYS_BOOTM_LEN SZ_128M
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]33#define CONFIG_SYS_LOAD_ADDR 0x82000000
34
35/*
36 * This board might be of different versions so handle it
37 */
38#define CONFIG_BOARD_TYPES
39
40/*
41 * UART configuration
42 */
43#define CONFIG_DW_SERIAL
44#define CONFIG_SYS_NS16550_SERIAL
45#define CONFIG_SYS_NS16550_CLK 33330000
46#define CONFIG_SYS_NS16550_MEM32
47
48/*
49 * Ethernet PHY configuration
50 */
51#define CONFIG_MII
52
53/*
54 * USB 1.1 configuration
55 */
56#define CONFIG_USB_OHCI_NEW
57#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
58
59/*
60 * Environment settings
61 */
62#define CONFIG_ENV_SIZE SZ_16K
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]63
Eugeniy Paltsev24e026e2018-03-26 15:57:37 +0300[diff] [blame]64#define CONFIG_EXTRA_ENV_SETTINGS \
65 "core_dccm_0=0x10\0" \
66 "core_dccm_1=0x6\0" \
67 "core_dccm_2=0x10\0" \
68 "core_dccm_3=0x6\0" \
69 "core_iccm_0=0x10\0" \
70 "core_iccm_1=0x6\0" \
71 "core_iccm_2=0x10\0" \
72 "core_iccm_3=0x6\0" \
73 "core_mask=0xF\0" \
74 "dcache_ena=0x1\0" \
75 "icache_ena=0x1\0" \
76 "non_volatile_limit=0xE\0" \
77 "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
78setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
79setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
80 "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
81setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
82setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
83 "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
84setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
85setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
86 "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
87setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
88setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
89 "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
90setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
91setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
92 "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
93setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
94setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
95setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
96 "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
97setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
98setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
99setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
100setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
101 "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
102setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
103setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
104setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
105setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
106setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
107
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]108/*
109 * Environment configuration
110 */
111#define CONFIG_BOOTFILE "uImage"
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]112#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
113
114/*
Eugeniy Paltsev24e026e2018-03-26 15:57:37 +0300[diff] [blame]115 * Misc utility configuration
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]116 */
Eugeniy Paltsev24e026e2018-03-26 15:57:37 +0300[diff] [blame]117#define CONFIG_BOUNCE_BUFFER
118
119/* Cli configuration */
120#define CONFIG_SYS_CBSIZE SZ_2K
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]121
122/*
Eugeniy Paltsev24e026e2018-03-26 15:57:37 +0300[diff] [blame]123 * Callback configuration
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]124 */
Eugeniy Paltsev24e026e2018-03-26 15:57:37 +0300[diff] [blame]125#define CONFIG_BOARD_LATE_INIT
Alexey Brodkin88961bc2016-11-25 16:23:43 +0300[diff] [blame]126
127#endif /* _CONFIG_HSDK_H_ */