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git01.mediatek.com / filogic / uboot / ca4d00e2e40dd5c623bb8b29a735b65fe5c51791 / . / drivers / net / ftgmac100.h
blob: ffbe1f3e3fa7aaa13ab3113458373c35ecb6c74b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Macpaul Lin199c6252010-12-21 16:59:46 +0800[diff] [blame]2/*
3 * Faraday FTGMAC100 Ethernet
4 *
5 * (C) Copyright 2010 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 *
8 * (C) Copyright 2010 Andes Technology
9 * Macpaul Lin <macpaul@andestech.com>
Macpaul Lin199c6252010-12-21 16:59:46 +0800[diff] [blame]10 */
11
12#ifndef __FTGMAC100_H
13#define __FTGMAC100_H
14
15/* The registers offset table of ftgmac100 */
16struct ftgmac100 {
17 unsigned int isr; /* 0x00 */
18 unsigned int ier; /* 0x04 */
19 unsigned int mac_madr; /* 0x08 */
20 unsigned int mac_ladr; /* 0x0c */
21 unsigned int maht0; /* 0x10 */
22 unsigned int maht1; /* 0x14 */
23 unsigned int txpd; /* 0x18 */
24 unsigned int rxpd; /* 0x1c */
25 unsigned int txr_badr; /* 0x20 */
26 unsigned int rxr_badr; /* 0x24 */
27 unsigned int hptxpd; /* 0x28 */
28 unsigned int hptxpd_badr; /* 0x2c */
29 unsigned int itc; /* 0x30 */
30 unsigned int aptc; /* 0x34 */
31 unsigned int dblac; /* 0x38 */
32 unsigned int dmafifos; /* 0x3c */
33 unsigned int revr; /* 0x40 */
34 unsigned int fear; /* 0x44 */
35 unsigned int tpafcr; /* 0x48 */
36 unsigned int rbsr; /* 0x4c */
37 unsigned int maccr; /* 0x50 */
38 unsigned int macsr; /* 0x54 */
39 unsigned int tm; /* 0x58 */
40 unsigned int resv1; /* 0x5c */ /* not defined in spec */
41 unsigned int phycr; /* 0x60 */
42 unsigned int phydata; /* 0x64 */
43 unsigned int fcr; /* 0x68 */
44 unsigned int bpr; /* 0x6c */
45 unsigned int wolcr; /* 0x70 */
46 unsigned int wolsr; /* 0x74 */
47 unsigned int wfcrc; /* 0x78 */
48 unsigned int resv2; /* 0x7c */ /* not defined in spec */
49 unsigned int wfbm1; /* 0x80 */
50 unsigned int wfbm2; /* 0x84 */
51 unsigned int wfbm3; /* 0x88 */
52 unsigned int wfbm4; /* 0x8c */
53 unsigned int nptxr_ptr; /* 0x90 */
54 unsigned int hptxr_ptr; /* 0x94 */
55 unsigned int rxr_ptr; /* 0x98 */
56 unsigned int resv3; /* 0x9c */ /* not defined in spec */
57 unsigned int tx; /* 0xa0 */
58 unsigned int tx_mcol_scol; /* 0xa4 */
59 unsigned int tx_ecol_fail; /* 0xa8 */
60 unsigned int tx_lcol_und; /* 0xac */
61 unsigned int rx; /* 0xb0 */
62 unsigned int rx_bc; /* 0xb4 */
63 unsigned int rx_mc; /* 0xb8 */
64 unsigned int rx_pf_aep; /* 0xbc */
65 unsigned int rx_runt; /* 0xc0 */
66 unsigned int rx_crcer_ftl; /* 0xc4 */
67 unsigned int rx_col_lost; /* 0xc8 */
68};
69
70/*
71 * Interrupt status register & interrupt enable register
72 */
73#define FTGMAC100_INT_RPKT_BUF (1 << 0)
74#define FTGMAC100_INT_RPKT_FIFO (1 << 1)
75#define FTGMAC100_INT_NO_RXBUF (1 << 2)
76#define FTGMAC100_INT_RPKT_LOST (1 << 3)
77#define FTGMAC100_INT_XPKT_ETH (1 << 4)
78#define FTGMAC100_INT_XPKT_FIFO (1 << 5)
79#define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
80#define FTGMAC100_INT_XPKT_LOST (1 << 7)
81#define FTGMAC100_INT_AHB_ERR (1 << 8)
82#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
83#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
84
85/*
86 * Interrupt timer control register
87 */
88#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
89#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
90#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7)
91#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
92#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
93#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15)
94
95/*
96 * Automatic polling timer control register
97 */
98#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
99#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
100#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
101#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
102
103/*
104 * DMA burst length and arbitration control register
105 */
106#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
107#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
108#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6)
109#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
110#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
111#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
112#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
113#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
114#define FTGMAC100_DBLAC_IFG_INC (1 << 23)
115
116/*
117 * DMA FIFO status register
118 */
119#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf)
120#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf)
121#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7)
122#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
123#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
124#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
125#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26)
126#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27)
127#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
128#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
129#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30)
130#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31)
131
132/*
133 * Receive buffer size register
134 */
135#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff)
136
137/*
138 * MAC control register
139 */
140#define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
141#define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
142#define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
143#define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
144#define FTGMAC100_MACCR_RM_VLAN (1 << 4)
145#define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
146#define FTGMAC100_MACCR_LOOP_EN (1 << 6)
147#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
148#define FTGMAC100_MACCR_FULLDUP (1 << 8)
149#define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
150#define FTGMAC100_MACCR_CRC_APD (1 << 10)
151#define FTGMAC100_MACCR_RX_RUNT (1 << 12)
152#define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
153#define FTGMAC100_MACCR_RX_ALL (1 << 14)
154#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
155#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
156#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
157#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
158#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
159#define FTGMAC100_MACCR_SW_RST (1 << 31)
160
161/*
162 * PHY control register
163 */
164#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f
165#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
166#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
167#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
168#define FTGMAC100_PHYCR_MIIRD (1 << 26)
169#define FTGMAC100_PHYCR_MIIWR (1 << 27)
170
171/*
172 * PHY data register
173 */
174#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
175#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff)
176
177/*
178 * Transmit descriptor, aligned to 16 bytes
179 */
180struct ftgmac100_txdes {
181 unsigned int txdes0;
182 unsigned int txdes1;
183 unsigned int txdes2; /* not used by HW */
184 unsigned int txdes3; /* TXBUF_BADR */
185} __attribute__ ((aligned(16)));
186
187#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
188#define FTGMAC100_TXDES0_EDOTR (1 << 15)
189#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
190#define FTGMAC100_TXDES0_LTS (1 << 28)
191#define FTGMAC100_TXDES0_FTS (1 << 29)
192#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
193
194#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
195#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
196#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
197#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
198#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
199#define FTGMAC100_TXDES1_LLC (1 << 22)
200#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
201#define FTGMAC100_TXDES1_TXIC (1 << 31)
202
203/*
204 * Receive descriptor, aligned to 16 bytes
205 */
206struct ftgmac100_rxdes {
207 unsigned int rxdes0;
208 unsigned int rxdes1;
209 unsigned int rxdes2; /* not used by HW */
210 unsigned int rxdes3; /* RXBUF_BADR */
211} __attribute__ ((aligned(16)));
212
213#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
214#define FTGMAC100_RXDES0_EDORR (1 << 15)
215#define FTGMAC100_RXDES0_MULTICAST (1 << 16)
216#define FTGMAC100_RXDES0_BROADCAST (1 << 17)
217#define FTGMAC100_RXDES0_RX_ERR (1 << 18)
218#define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
219#define FTGMAC100_RXDES0_FTL (1 << 20)
220#define FTGMAC100_RXDES0_RUNT (1 << 21)
221#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
222#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
223#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
224#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
225#define FTGMAC100_RXDES0_LRS (1 << 28)
226#define FTGMAC100_RXDES0_FRS (1 << 29)
227#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
228
229#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
230#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
231#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
232#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
233#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
234#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
235#define FTGMAC100_RXDES1_LLC (1 << 22)
236#define FTGMAC100_RXDES1_DF (1 << 23)
237#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
238#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
239#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
240#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
241
242#endif /* __FTGMAC100_H */