blob: 478ca50a89423d88b3dfde6526913ac0bf52d18f [file] [log] [blame]
Peter Tyseredb9d592009-06-30 17:26:01 -05001/*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Peter Tyseredb9d592009-06-30 17:26:01 -05006 */
7
8/*
Peter Tyser6ae37062010-10-22 00:20:26 -05009 * xpedite517x board configuration file
Peter Tyseredb9d592009-06-30 17:26:01 -050010 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 */
Peter Tyseredb9d592009-06-30 17:26:01 -050017#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
18#define CONFIG_SYS_BOARD_NAME "XPedite5170"
John Schmollerd9c2dd52010-10-22 00:20:24 -050019#define CONFIG_SYS_FORM_3U_VPX 1
Peter Tyseredb9d592009-06-30 17:26:01 -050020#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
21#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
Peter Tyser86dee4a2010-10-07 22:32:48 -050022#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Peter Tyseredb9d592009-06-30 17:26:01 -050023#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
24#define CONFIG_ALTIVEC 1
25
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0xfff00000
27
Peter Tyseredb9d592009-06-30 17:26:01 -050028#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
Robert P. J. Daya8099812016-05-03 19:52:49 -040029#define CONFIG_PCIE1 1 /* PCIE controller 1 */
30#define CONFIG_PCIE2 1 /* PCIE controller 2 */
Peter Tyseredb9d592009-06-30 17:26:01 -050031#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhosb4458732013-05-30 07:06:12 +000032#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Peter Tyseredb9d592009-06-30 17:26:01 -050033#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Peter Tyseredb9d592009-06-30 17:26:01 -050034
35/*
36 * DDR config
37 */
Peter Tyseredb9d592009-06-30 17:26:01 -050038#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
39#define CONFIG_DDR_SPD
40#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
41#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
42#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
43#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
Peter Tyseredb9d592009-06-30 17:26:01 -050044#define CONFIG_DIMM_SLOTS_PER_CTLR 1
45#define CONFIG_CHIP_SELECTS_PER_CTRL 1
46#define CONFIG_DDR_ECC
47#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
49#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
50#define CONFIG_VERY_BIG_RAM
51#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
52
53/*
54 * virtual address to be used for temporary mappings. There
55 * should be 128k free at this VA.
56 */
57#define CONFIG_SYS_SCRATCH_VA 0xe0000000
58
59#ifndef __ASSEMBLY__
60extern unsigned long get_board_sys_clk(unsigned long dummy);
61#endif
62
63#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
64
65/*
66 * L2CR setup
67 */
68#define CONFIG_SYS_L2
69#define L2_INIT 0
70#define L2_ENABLE (L2CR_L2E)
71
72/*
73 * Base addresses -- Note these are effective addresses where the
74 * actual resources get mapped (not physical addresses)
75 */
Peter Tyseredb9d592009-06-30 17:26:01 -050076#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
77#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
78#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
79#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
80#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
Peter Tyseredb9d592009-06-30 17:26:01 -050081
82/*
83 * Diagnostics
84 */
85#define CONFIG_SYS_ALT_MEMTEST
86#define CONFIG_SYS_MEMTEST_START 0x10000000
87#define CONFIG_SYS_MEMTEST_END 0x20000000
Peter Tysera9585322010-10-22 00:20:33 -050088#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
89 CONFIG_SYS_POST_I2C)
Peter Tysera9585322010-10-22 00:20:33 -050090/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
91#define I2C_ADDR_IGNORE_LIST {0x50}
Peter Tyseredb9d592009-06-30 17:26:01 -050092
93/*
94 * Memory map
95 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
96 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
97 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
98 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
99 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
100 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
101 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
102 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
103 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
104 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
105 */
106
Kumar Gala6fa11c12009-09-15 22:21:58 -0500107#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
Peter Tyseredb9d592009-06-30 17:26:01 -0500108
109/*
110 * NAND flash configuration
111 */
112#define CONFIG_SYS_NAND_BASE 0xef800000
113#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
114#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
115#define CONFIG_SYS_MAX_NAND_DEVICE 2
116#define CONFIG_NAND_ACTL
117#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
118#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
119#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
120#define CONFIG_SYS_NAND_ACTL_DELAY 25
Peter Tyseredb9d592009-06-30 17:26:01 -0500121#define CONFIG_JFFS2_NAND
122
123/*
124 * NOR flash configuration
125 */
126#define CONFIG_SYS_FLASH_BASE 0xf8000000
127#define CONFIG_SYS_FLASH_BASE2 0xf0000000
128#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
129#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
130#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
131#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
132#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
133#define CONFIG_FLASH_CFI_DRIVER
134#define CONFIG_SYS_FLASH_CFI
135#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
136#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
137 {0xf7f00000, 0xc0000} }
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200138#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Peter Tyseredb9d592009-06-30 17:26:01 -0500139#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
140
141/*
142 * Chip select configuration
143 */
144/* NOR Flash 0 on CS0 */
145#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
146 BR_PS_16 |\
147 BR_V)
148#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
149 OR_GPCM_CSNT |\
150 OR_GPCM_XACS |\
151 OR_GPCM_ACS_DIV2 |\
152 OR_GPCM_SCY_8 |\
153 OR_GPCM_TRLX |\
154 OR_GPCM_EHTR |\
155 OR_GPCM_EAD)
156
157/* NOR Flash 1 on CS1 */
158#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
159 BR_PS_16 |\
160 BR_V)
161#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
162
163/* NAND flash on CS2 */
164#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
165 BR_PS_8 |\
166 BR_V)
167#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
168 OR_GPCM_BCTLD |\
169 OR_GPCM_CSNT |\
170 OR_GPCM_ACS_DIV4 |\
171 OR_GPCM_SCY_4 |\
172 OR_GPCM_TRLX |\
173 OR_GPCM_EHTR)
174
175/* Optional NAND flash on CS3 */
176#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
177 BR_PS_8 |\
178 BR_V)
179#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
180
181/*
182 * Use L1 as initial stack
183 */
184#define CONFIG_SYS_INIT_RAM_LOCK 1
185#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200186#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
Peter Tyseredb9d592009-06-30 17:26:01 -0500187
Wolfgang Denk0191e472010-10-26 14:34:52 +0200188#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Peter Tyseredb9d592009-06-30 17:26:01 -0500189#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
190
191#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
192#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
193
194/*
195 * Serial Port
196 */
197#define CONFIG_CONS_INDEX 1
Peter Tyseredb9d592009-06-30 17:26:01 -0500198#define CONFIG_SYS_NS16550_SERIAL
199#define CONFIG_SYS_NS16550_REG_SIZE 1
200#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
201#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
202#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
203#define CONFIG_SYS_BAUDRATE_TABLE \
204 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Peter Tyseredb9d592009-06-30 17:26:01 -0500205#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
206#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
207
208/*
Peter Tyseredb9d592009-06-30 17:26:01 -0500209 * I2C
210 */
Heiko Schocherf2850742012-10-24 13:48:22 +0200211#define CONFIG_SYS_I2C
212#define CONFIG_SYS_I2C_FSL
213#define CONFIG_SYS_FSL_I2C_SPEED 100000
214#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
215#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
216#define CONFIG_SYS_FSL_I2C2_SPEED 100000
217#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
218#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Peter Tyseredb9d592009-06-30 17:26:01 -0500219
220/* PEX8518 slave I2C interface */
221#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
222
223/* I2C DS1631 temperature sensor */
Peter Tysera9585322010-10-22 00:20:33 -0500224#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
Peter Tyseredb9d592009-06-30 17:26:01 -0500225
226/* I2C EEPROM - AT24C128B */
227#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
228#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
229#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
230#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
231
232/* I2C RTC */
233#define CONFIG_RTC_M41T11 1
234#define CONFIG_SYS_I2C_RTC_ADDR 0x68
235#define CONFIG_SYS_M41T11_BASE_YEAR 2000
236
Peter Tyseredb9d592009-06-30 17:26:01 -0500237/* GPIO */
238#define CONFIG_PCA953X
239#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
240#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
241#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
242#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
243#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
Peter Tysera9585322010-10-22 00:20:33 -0500244#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
Peter Tyseredb9d592009-06-30 17:26:01 -0500245
246/*
247 * PU = pulled high, PD = pulled low
248 * I = input, O = output, IO = input/output
249 */
250/* PCA9557 @ 0x18*/
251#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
252#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
253#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
254#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
255#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
256#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
257
258/* PCA9557 @ 0x1c*/
259#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
260#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
261#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
262#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
263#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
264#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
265#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
266#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
267
268/* PCA9557 @ 0x1e*/
269#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
270#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
271#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
272#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
273#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
274#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
275#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
276
277/* PCA9557 @ 0x1f */
278#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
279#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
280#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
281#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
282
283/*
284 * General PCI
285 * Memory space is mapped 1-1, but I/O space must start from 0.
286 */
287/* PCIE1 - PEX8518 */
Peter Tyser51944772010-10-22 00:20:22 -0500288#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
289#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Peter Tyseredb9d592009-06-30 17:26:01 -0500290#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
Peter Tyser51944772010-10-22 00:20:22 -0500291#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Peter Tyseredb9d592009-06-30 17:26:01 -0500292#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
293#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
294
295/* PCIE2 - VPX P1 */
Peter Tyser51944772010-10-22 00:20:22 -0500296#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
297#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
Peter Tyseredb9d592009-06-30 17:26:01 -0500298#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
Peter Tyser51944772010-10-22 00:20:22 -0500299#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Peter Tyseredb9d592009-06-30 17:26:01 -0500300#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
301#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
302
303/*
304 * Networking options
305 */
306#define CONFIG_TSEC_ENET /* tsec ethernet support */
Peter Tyseredb9d592009-06-30 17:26:01 -0500307#define CONFIG_MII 1 /* MII PHY management */
308#define CONFIG_ETHPRIME "eTSEC1"
309
310#define CONFIG_TSEC1 1
311#define CONFIG_TSEC1_NAME "eTSEC1"
312#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
313#define TSEC1_PHY_ADDR 1
314#define TSEC1_PHYIDX 0
315#define CONFIG_HAS_ETH0
316
317#define CONFIG_TSEC2 1
318#define CONFIG_TSEC2_NAME "eTSEC2"
319#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
320#define TSEC2_PHY_ADDR 2
321#define TSEC2_PHYIDX 0
322#define CONFIG_HAS_ETH1
323
324/*
325 * BAT mappings
326 */
327#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
328#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
329 BATL_PP_RW |\
330 BATL_CACHEINHIBIT |\
331 BATL_GUARDEDSTORAGE)
332#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
333 BATU_BL_1M |\
334 BATU_VS |\
335 BATU_VP)
336#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
337 BATL_PP_RW |\
338 BATL_CACHEINHIBIT)
339#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
340#endif
341
342/*
343 * BAT0 2G Cacheable, non-guarded
344 * 0x0000_0000 2G DDR
345 */
346#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
347#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
348#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
349#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
350
351/*
352 * BAT1 1G Cache-inhibited, guarded
353 * 0x8000_0000 1G PCI-Express 1 Memory
354 */
355#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
356 BATL_PP_RW |\
357 BATL_CACHEINHIBIT |\
358 BATL_GUARDEDSTORAGE)
359#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
360 BATU_BL_1G |\
361 BATU_VS |\
362 BATU_VP)
363#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
364 BATL_PP_RW |\
365 BATL_CACHEINHIBIT)
366#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
367
368/*
369 * BAT2 512M Cache-inhibited, guarded
370 * 0xc000_0000 512M PCI-Express 2 Memory
371 */
372#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
373 BATL_PP_RW |\
374 BATL_CACHEINHIBIT |\
375 BATL_GUARDEDSTORAGE)
376#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
377 BATU_BL_512M |\
378 BATU_VS |\
379 BATU_VP)
380#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
381 BATL_PP_RW |\
382 BATL_CACHEINHIBIT)
383#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
384
385/*
386 * BAT3 1M Cache-inhibited, guarded
387 * 0xe000_0000 1M CCSR
388 */
389#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
390 BATL_PP_RW |\
391 BATL_CACHEINHIBIT |\
392 BATL_GUARDEDSTORAGE)
393#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
394 BATU_BL_1M |\
395 BATU_VS |\
396 BATU_VP)
397#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
398 BATL_PP_RW |\
399 BATL_CACHEINHIBIT)
400#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
401
402/*
403 * BAT4 32M Cache-inhibited, guarded
404 * 0xe200_0000 16M PCI-Express 1 I/O
405 * 0xe300_0000 16M PCI-Express 2 I/0
406 */
407#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
408 BATL_PP_RW |\
409 BATL_CACHEINHIBIT |\
410 BATL_GUARDEDSTORAGE)
411#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
412 BATU_BL_32M |\
413 BATU_VS |\
414 BATU_VP)
415#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
416 BATL_PP_RW |\
417 BATL_CACHEINHIBIT)
418#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
419
420/*
421 * BAT5 128K Cacheable, non-guarded
422 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
423 */
424#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
425 BATL_PP_RW |\
426 BATL_MEMCOHERENCE)
427#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
428 BATU_BL_128K |\
429 BATU_VS |\
430 BATU_VP)
431#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
432#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
433
434/*
435 * BAT6 256M Cache-inhibited, guarded
436 * 0xf000_0000 256M FLASH
437 */
438#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
439 BATL_PP_RW |\
440 BATL_CACHEINHIBIT |\
441 BATL_GUARDEDSTORAGE)
442#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
443 BATU_BL_256M |\
444 BATU_VS |\
445 BATU_VP)
446#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
447 BATL_PP_RW |\
448 BATL_MEMCOHERENCE)
449#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
450
451/* Map the last 1M of flash where we're running from reset */
452#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
453 BATL_PP_RW |\
454 BATL_CACHEINHIBIT |\
455 BATL_GUARDEDSTORAGE)
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200456#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
Peter Tyseredb9d592009-06-30 17:26:01 -0500457 BATU_BL_1M |\
458 BATU_VS |\
459 BATU_VP)
460#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
461 BATL_PP_RW |\
462 BATL_MEMCOHERENCE)
463#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
464
465/*
466 * BAT7 64M Cache-inhibited, guarded
467 * 0xe800_0000 64K NAND FLASH
468 * 0xe804_0000 128K DUART Registers
469 */
470#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
471 BATL_PP_RW |\
472 BATL_CACHEINHIBIT |\
473 BATL_GUARDEDSTORAGE)
474#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
475 BATU_BL_512K |\
476 BATU_VS |\
477 BATU_VP)
478#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
479 BATL_PP_RW |\
480 BATL_CACHEINHIBIT)
481#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
482
483/*
484 * Command configuration.
485 */
Peter Tyseredb9d592009-06-30 17:26:01 -0500486#define CONFIG_CMD_PCA953X
487#define CONFIG_CMD_PCA953X_INFO
488#define CONFIG_CMD_PCI
John Schmoller60e877f2010-10-22 00:20:23 -0500489#define CONFIG_CMD_PCI_ENUM
Peter Tyseredb9d592009-06-30 17:26:01 -0500490#define CONFIG_CMD_REGINFO
Peter Tyseredb9d592009-06-30 17:26:01 -0500491
492/*
493 * Miscellaneous configurable options
494 */
495#define CONFIG_SYS_LONGHELP /* undef to save memory */
496#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Peter Tyseredb9d592009-06-30 17:26:01 -0500497#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
498#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
499#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
500#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Peter Tyseredb9d592009-06-30 17:26:01 -0500501#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
502#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
Peter Tyseredb9d592009-06-30 17:26:01 -0500503#define CONFIG_PANIC_HANG /* do not reset board on panic */
504#define CONFIG_PREBOOT /* enable preboot variable */
Peter Tyseredb9d592009-06-30 17:26:01 -0500505#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
506
507/*
508 * For booting Linux, the board info and command line data
509 * have to be in the first 16 MB of memory, since this is
510 * the maximum mapped by the Linux kernel during initialization.
511 */
512#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser3744c402009-07-21 13:51:07 -0500513#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyseredb9d592009-06-30 17:26:01 -0500514
515/*
Peter Tyseredb9d592009-06-30 17:26:01 -0500516 * Environment Configuration
517 */
Peter Tyseredb9d592009-06-30 17:26:01 -0500518#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
519#define CONFIG_ENV_SIZE 0x8000
520#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
521
522/*
523 * Flash memory map:
524 * fffc0000 - ffffffff Pri FDT (256KB)
525 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
526 * fff00000 - fff7ffff Pri U-Boot (512 KB)
527 * fef00000 - ffefffff Pri OS image (16MB)
528 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
529 *
530 * f7fc0000 - f7ffffff Sec FDT (256KB)
531 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
532 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
533 * f6f00000 - f7efffff Sec OS image (16MB)
534 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
535 */
Marek Vasut0b3176c2012-09-23 17:41:24 +0200536#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
537#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
538#define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
539#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
540#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
541#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
Peter Tyseredb9d592009-06-30 17:26:01 -0500542
543#define CONFIG_PROG_UBOOT1 \
544 "$download_cmd $loadaddr $ubootfile; " \
545 "if test $? -eq 0; then " \
546 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
547 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
548 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
549 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
550 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
551 "if test $? -ne 0; then " \
552 "echo PROGRAM FAILED; " \
553 "else; " \
554 "echo PROGRAM SUCCEEDED; " \
555 "fi; " \
556 "else; " \
557 "echo DOWNLOAD FAILED; " \
558 "fi;"
559
560#define CONFIG_PROG_UBOOT2 \
561 "$download_cmd $loadaddr $ubootfile; " \
562 "if test $? -eq 0; then " \
563 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
564 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
565 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
566 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
567 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
568 "if test $? -ne 0; then " \
569 "echo PROGRAM FAILED; " \
570 "else; " \
571 "echo PROGRAM SUCCEEDED; " \
572 "fi; " \
573 "else; " \
574 "echo DOWNLOAD FAILED; " \
575 "fi;"
576
577#define CONFIG_BOOT_OS_NET \
578 "$download_cmd $osaddr $osfile; " \
579 "if test $? -eq 0; then " \
580 "if test -n $fdtaddr; then " \
581 "$download_cmd $fdtaddr $fdtfile; " \
582 "if test $? -eq 0; then " \
583 "bootm $osaddr - $fdtaddr; " \
584 "else; " \
585 "echo FDT DOWNLOAD FAILED; " \
586 "fi; " \
587 "else; " \
588 "bootm $osaddr; " \
589 "fi; " \
590 "else; " \
591 "echo OS DOWNLOAD FAILED; " \
592 "fi;"
593
594#define CONFIG_PROG_OS1 \
595 "$download_cmd $osaddr $osfile; " \
596 "if test $? -eq 0; then " \
597 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
598 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
599 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
600 "if test $? -ne 0; then " \
601 "echo OS PROGRAM FAILED; " \
602 "else; " \
603 "echo OS PROGRAM SUCCEEDED; " \
604 "fi; " \
605 "else; " \
606 "echo OS DOWNLOAD FAILED; " \
607 "fi;"
608
609#define CONFIG_PROG_OS2 \
610 "$download_cmd $osaddr $osfile; " \
611 "if test $? -eq 0; then " \
612 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
613 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
614 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
615 "if test $? -ne 0; then " \
616 "echo OS PROGRAM FAILED; " \
617 "else; " \
618 "echo OS PROGRAM SUCCEEDED; " \
619 "fi; " \
620 "else; " \
621 "echo OS DOWNLOAD FAILED; " \
622 "fi;"
623
624#define CONFIG_PROG_FDT1 \
625 "$download_cmd $fdtaddr $fdtfile; " \
626 "if test $? -eq 0; then " \
627 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
628 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
629 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
630 "if test $? -ne 0; then " \
631 "echo FDT PROGRAM FAILED; " \
632 "else; " \
633 "echo FDT PROGRAM SUCCEEDED; " \
634 "fi; " \
635 "else; " \
636 "echo FDT DOWNLOAD FAILED; " \
637 "fi;"
638
639#define CONFIG_PROG_FDT2 \
640 "$download_cmd $fdtaddr $fdtfile; " \
641 "if test $? -eq 0; then " \
642 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
643 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
644 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
645 "if test $? -ne 0; then " \
646 "echo FDT PROGRAM FAILED; " \
647 "else; " \
648 "echo FDT PROGRAM SUCCEEDED; " \
649 "fi; " \
650 "else; " \
651 "echo FDT DOWNLOAD FAILED; " \
652 "fi;"
653
654#define CONFIG_EXTRA_ENV_SETTINGS \
655 "autoload=yes\0" \
656 "download_cmd=tftp\0" \
657 "console_args=console=ttyS0,115200\0" \
658 "root_args=root=/dev/nfs rw\0" \
659 "misc_args=ip=on\0" \
660 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
661 "bootfile=/home/user/file\0" \
Peter Tyser6ae37062010-10-22 00:20:26 -0500662 "osfile=/home/user/board.uImage\0" \
663 "fdtfile=/home/user/board.dtb\0" \
Peter Tyseredb9d592009-06-30 17:26:01 -0500664 "ubootfile=/home/user/u-boot.bin\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500665 "fdtaddr=0x1e00000\0" \
Peter Tyseredb9d592009-06-30 17:26:01 -0500666 "osaddr=0x1000000\0" \
667 "loadaddr=0x1000000\0" \
668 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
669 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
670 "prog_os1="CONFIG_PROG_OS1"\0" \
671 "prog_os2="CONFIG_PROG_OS2"\0" \
672 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
673 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
674 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
675 "bootcmd_flash1=run set_bootargs; " \
676 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
677 "bootcmd_flash2=run set_bootargs; " \
678 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
679 "bootcmd=run bootcmd_flash1\0"
680#endif /* __CONFIG_H */