blob: a62d1d325478f2c6f300526a4ca08992fab89fa4 [file] [log] [blame]
Masami Hiramatsu7c741272021-06-04 18:45:10 +09001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2017 Socionext Inc.
4 */
5#ifndef __CONFIG_H
6#define __CONFIG_H
7
8/* Timers for fasp(TIMCLK) */
Tom Rini6a5dccc2022-11-16 13:10:41 -05009#define CFG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
Masami Hiramatsu7c741272021-06-04 18:45:10 +090010
11/*
12 * SDRAM (for initialize)
13 */
Tom Rinibb4dd962022-11-16 13:10:37 -050014#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
Masami Hiramatsu7c741272021-06-04 18:45:10 +090015#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
16
Masami Hiramatsu7c741272021-06-04 18:45:10 +090017#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
18
19#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
20
21/*
22 * Boot info
23 */
Masami Hiramatsu7c741272021-06-04 18:45:10 +090024
25/*
26 * Hardware drivers support
27 */
28
29/* RTC */
Tom Rini6a5dccc2022-11-16 13:10:41 -050030#define CFG_SYS_I2C_RTC_ADDR 0x51
Masami Hiramatsu7c741272021-06-04 18:45:10 +090031
32/* Serial (pl011) */
33#define UART_CLK (62500000)
Masami Hiramatsu7c741272021-06-04 18:45:10 +090034#define CONFIG_PL011_CLOCK UART_CLK
35#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
36
Masami Hiramatsu7c741272021-06-04 18:45:10 +090037/* Support MTD */
Tom Rini6a5dccc2022-11-16 13:10:41 -050038#define CFG_SYS_FLASH_BASE (0x08000000)
39#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE}
Masami Hiramatsu7c741272021-06-04 18:45:10 +090040
Masami Hiramatsu7c741272021-06-04 18:45:10 +090041/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
Masami Hiramatsu7c741272021-06-04 18:45:10 +090042
Masami Hiramatsu1d5afdf2021-06-04 18:45:31 +090043#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
Masami Hiramatsu88f0d1d2021-11-10 09:40:07 +090044 "mtd nor1=u-boot.bin raw 200000 100000;" \
Masami Hiramatsu1d5afdf2021-06-04 18:45:31 +090045 "fip.bin raw 180000 78000;" \
46 "optee.bin raw 500000 100000\0"
47
Sughosh Ganuccb36462022-04-15 11:29:34 +053048/* GUIDs for capsule updatable firmware images */
49#define DEVELOPERBOX_UBOOT_IMAGE_GUID \
50 EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \
51 0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00)
52
53#define DEVELOPERBOX_FIP_IMAGE_GUID \
54 EFI_GUID(0x880866e9, 0x84ba, 0x4793, 0xa9, 0x08, \
55 0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98)
56
57#define DEVELOPERBOX_OPTEE_IMAGE_GUID \
58 EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \
59 0xf0, 0xa3, 0x83, 0x87, 0xe6, 0x30)
60
Masami Hiramatsu7c741272021-06-04 18:45:10 +090061/* Distro boot settings */
Masami Hiramatsu7c741272021-06-04 18:45:10 +090062#ifdef CONFIG_CMD_USB
63#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
64#else
65#define BOOT_TARGET_DEVICE_USB(func)
66#endif
67
68#ifdef CONFIG_CMD_MMC
69#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
70#else
71#define BOOT_TARGET_DEVICE_MMC(func)
72#endif
73
74#ifdef CONFIG_CMD_NVME
75#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
76#else
77#define BOOT_TARGET_DEVICE_NVME(func)
78#endif
79
80#ifdef CONFIG_CMD_SCSI
81#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
82#else
83#define BOOT_TARGET_DEVICE_SCSI(func)
84#endif
85
86#define BOOT_TARGET_DEVICES(func) \
87 BOOT_TARGET_DEVICE_USB(func) \
88 BOOT_TARGET_DEVICE_MMC(func) \
89 BOOT_TARGET_DEVICE_SCSI(func) \
90 BOOT_TARGET_DEVICE_NVME(func) \
91
92#include <config_distro_bootcmd.h>
Masami Hiramatsu7c741272021-06-04 18:45:10 +090093
Tom Rinic9edebe2022-12-04 10:03:50 -050094#define CFG_EXTRA_ENV_SETTINGS \
Masami Hiramatsu7c741272021-06-04 18:45:10 +090095 "fdt_addr_r=0x9fe00000\0" \
96 "kernel_addr_r=0x90000000\0" \
97 "ramdisk_addr_r=0xa0000000\0" \
98 "scriptaddr=0x88000000\0" \
99 "pxefile_addr_r=0x88100000\0" \
Masami Hiramatsu1d5afdf2021-06-04 18:45:31 +0900100 DEFAULT_DFU_ALT_INFO \
Masami Hiramatsu7c741272021-06-04 18:45:10 +0900101 BOOTENV
102
103#endif /* __CONFIG_H */