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wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +00006 *
wdenkb00ec162003-06-19 23:40:20 +00007 * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
wdenkaffae2b2002-08-17 09:36:01 +00008 */
9
10#include <common.h>
11#include <mpc8260.h>
12#include <board/hymod/flash.h>
13
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020014flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
wdenkaffae2b2002-08-17 09:36:01 +000015
16/*-----------------------------------------------------------------------
17 * Protection Flags:
18 */
19#define FLAG_PROTECT_SET 0x01
20#define FLAG_PROTECT_CLEAR 0x02
21
22/*-----------------------------------------------------------------------
wdenkaffae2b2002-08-17 09:36:01 +000023 */
wdenkaffae2b2002-08-17 09:36:01 +000024
25/*
wdenkb00ec162003-06-19 23:40:20 +000026 * probe for flash bank at address "base" and store info about it
27 * in the flash_info entry "fip". Fatal error if nothing there.
wdenkaffae2b2002-08-17 09:36:01 +000028 */
wdenkb00ec162003-06-19 23:40:20 +000029static void
wdenkdbae5042003-06-21 00:17:24 +000030bank_probe (flash_info_t *fip, volatile bank_addr_t base)
wdenkaffae2b2002-08-17 09:36:01 +000031{
wdenkdbae5042003-06-21 00:17:24 +000032 volatile bank_addr_t addr;
wdenkb00ec162003-06-19 23:40:20 +000033 bank_word_t word;
34 int i;
wdenkaffae2b2002-08-17 09:36:01 +000035
36 /* reset the flash */
wdenkb00ec162003-06-19 23:40:20 +000037 *base = BANK_CMD_RST;
wdenkaffae2b2002-08-17 09:36:01 +000038
wdenkdbae5042003-06-21 00:17:24 +000039 /* put flash into read id mode */
wdenkb00ec162003-06-19 23:40:20 +000040 *base = BANK_CMD_RD_ID;
wdenkaffae2b2002-08-17 09:36:01 +000041
wdenkdbae5042003-06-21 00:17:24 +000042 /* check the manufacturer id - must be intel */
43 word = *BANK_REG_MAN_CODE (base);
wdenkb00ec162003-06-19 23:40:20 +000044 if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff))
45 panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx",
46 (unsigned long)word, (unsigned long)base);
wdenkaffae2b2002-08-17 09:36:01 +000047
wdenkb00ec162003-06-19 23:40:20 +000048 /* check the device id */
wdenkb00ec162003-06-19 23:40:20 +000049 word = *BANK_REG_DEV_CODE (base);
wdenkb00ec162003-06-19 23:40:20 +000050 switch (word) {
wdenkaffae2b2002-08-17 09:36:01 +000051
wdenkb00ec162003-06-19 23:40:20 +000052 case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff):
53 fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5;
54 fip->sector_count = 32;
55 break;
wdenkaffae2b2002-08-17 09:36:01 +000056
wdenkb00ec162003-06-19 23:40:20 +000057 case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff):
58 fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5;
59 fip->sector_count = 64;
60 break;
wdenkaffae2b2002-08-17 09:36:01 +000061
wdenkb00ec162003-06-19 23:40:20 +000062 case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff):
63 fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A;
64 fip->sector_count = 32;
65 break;
wdenkaffae2b2002-08-17 09:36:01 +000066
wdenkb00ec162003-06-19 23:40:20 +000067 case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff):
68 fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A;
69 fip->sector_count = 64;
70 break;
wdenkaffae2b2002-08-17 09:36:01 +000071
wdenkb00ec162003-06-19 23:40:20 +000072 case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff):
73 fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A;
74 fip->sector_count = 128;
75 break;
wdenkaffae2b2002-08-17 09:36:01 +000076
wdenkb00ec162003-06-19 23:40:20 +000077 default:
78 panic ("\nbad device code (0x%08lx) at addr 0x%08lx",
79 (unsigned long)word, (unsigned long)base);
80 }
wdenkaffae2b2002-08-17 09:36:01 +000081
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082 if (fip->sector_count >= CONFIG_SYS_MAX_FLASH_SECT)
wdenkb00ec162003-06-19 23:40:20 +000083 panic ("\ntoo many sectors (%d) in flash at address 0x%08lx",
84 fip->sector_count, (unsigned long)base);
wdenkaffae2b2002-08-17 09:36:01 +000085
wdenkb00ec162003-06-19 23:40:20 +000086 addr = base;
87 for (i = 0; i < fip->sector_count; i++) {
88 fip->start[i] = (unsigned long)addr;
89 fip->protect[i] = 0;
90 addr = BANK_ADDR_NEXT_BLK (addr);
wdenkaffae2b2002-08-17 09:36:01 +000091 }
92
wdenkb00ec162003-06-19 23:40:20 +000093 fip->size = (bank_size_t)addr - (bank_size_t)base;
wdenkdbae5042003-06-21 00:17:24 +000094
95 /* reset the flash */
96 *base = BANK_CMD_RST;
wdenkaffae2b2002-08-17 09:36:01 +000097}
98
99static void
wdenkb00ec162003-06-19 23:40:20 +0000100bank_reset (flash_info_t *info, int sect)
wdenkaffae2b2002-08-17 09:36:01 +0000101{
wdenkdbae5042003-06-21 00:17:24 +0000102 volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
wdenkaffae2b2002-08-17 09:36:01 +0000103
wdenkaffae2b2002-08-17 09:36:01 +0000104#ifdef FLASH_DEBUG
wdenkb00ec162003-06-19 23:40:20 +0000105 printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr);
wdenkaffae2b2002-08-17 09:36:01 +0000106#endif
wdenkb00ec162003-06-19 23:40:20 +0000107
108 *addr = BANK_CMD_RST;
wdenkaffae2b2002-08-17 09:36:01 +0000109}
110
111static void
wdenkb00ec162003-06-19 23:40:20 +0000112bank_erase_init (flash_info_t *info, int sect)
wdenkaffae2b2002-08-17 09:36:01 +0000113{
wdenkdbae5042003-06-21 00:17:24 +0000114 volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
wdenkaffae2b2002-08-17 09:36:01 +0000115 int flag;
116
117#ifdef FLASH_DEBUG
wdenkb00ec162003-06-19 23:40:20 +0000118 printf ("erasing sector %d, addr = 0x%08lx\n",
119 sect, (unsigned long)addr);
wdenkaffae2b2002-08-17 09:36:01 +0000120#endif
121
wdenkaffae2b2002-08-17 09:36:01 +0000122 /* Disable intrs which might cause a timeout here */
wdenkb00ec162003-06-19 23:40:20 +0000123 flag = disable_interrupts ();
wdenkaffae2b2002-08-17 09:36:01 +0000124
wdenkaffae2b2002-08-17 09:36:01 +0000125#ifdef FLASH_DEBUG
wdenkb00ec162003-06-19 23:40:20 +0000126 printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr);
wdenkaffae2b2002-08-17 09:36:01 +0000127#endif
wdenkb00ec162003-06-19 23:40:20 +0000128 *addr = BANK_CMD_ERASE1;
129 *addr = BANK_CMD_ERASE2;
wdenkaffae2b2002-08-17 09:36:01 +0000130
131 /* re-enable interrupts if necessary */
132 if (flag)
wdenkb00ec162003-06-19 23:40:20 +0000133 enable_interrupts ();
wdenkaffae2b2002-08-17 09:36:01 +0000134}
135
136static int
wdenkb00ec162003-06-19 23:40:20 +0000137bank_erase_poll (flash_info_t *info, int sect)
wdenkaffae2b2002-08-17 09:36:01 +0000138{
wdenkdbae5042003-06-21 00:17:24 +0000139 volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
wdenkb00ec162003-06-19 23:40:20 +0000140 bank_word_t stat = *addr;
wdenkaffae2b2002-08-17 09:36:01 +0000141
142#ifdef FLASH_DEBUG
wdenkb00ec162003-06-19 23:40:20 +0000143 printf ("checking status at addr 0x%08lx [0x%08lx]\n",
144 (unsigned long)addr, (unsigned long)stat);
wdenkaffae2b2002-08-17 09:36:01 +0000145#endif
wdenkb00ec162003-06-19 23:40:20 +0000146
147 if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) {
148 if ((stat & BANK_STAT_ERR) != 0) {
149 printf ("failed on sector %d [0x%08lx] at "
150 "address 0x%08lx\n", sect,
151 (unsigned long)stat, (unsigned long)addr);
152 *addr = BANK_CMD_CLR_STAT;
153 return (-1);
wdenkaffae2b2002-08-17 09:36:01 +0000154 }
wdenkb00ec162003-06-19 23:40:20 +0000155 else
156 return (1);
wdenkaffae2b2002-08-17 09:36:01 +0000157 }
wdenkaffae2b2002-08-17 09:36:01 +0000158 else
wdenkb00ec162003-06-19 23:40:20 +0000159 return (0);
wdenkaffae2b2002-08-17 09:36:01 +0000160}
161
162static int
wdenkdbae5042003-06-21 00:17:24 +0000163bank_write_word (volatile bank_addr_t addr, bank_word_t value)
wdenkaffae2b2002-08-17 09:36:01 +0000164{
165 bank_word_t stat;
166 ulong start;
167 int flag, retval;
168
169 /* Disable interrupts which might cause a timeout here */
wdenkb00ec162003-06-19 23:40:20 +0000170 flag = disable_interrupts ();
wdenkaffae2b2002-08-17 09:36:01 +0000171
172 *addr = BANK_CMD_PROG;
173
174 *addr = value;
175
176 /* re-enable interrupts if necessary */
177 if (flag)
wdenkb00ec162003-06-19 23:40:20 +0000178 enable_interrupts ();
wdenkaffae2b2002-08-17 09:36:01 +0000179
180 retval = 0;
181
182 /* data polling for D7 */
183 start = get_timer (0);
184 do {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185 if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
wdenkaffae2b2002-08-17 09:36:01 +0000186 retval = 1;
187 goto done;
188 }
189 stat = *addr;
190 } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
191
192 if ((stat & BANK_STAT_ERR) != 0) {
wdenkb00ec162003-06-19 23:40:20 +0000193 printf ("flash program failed [0x%08lx] at address 0x%08lx\n",
194 (unsigned long)stat, (unsigned long)addr);
wdenkaffae2b2002-08-17 09:36:01 +0000195 *addr = BANK_CMD_CLR_STAT;
196 retval = 3;
197 }
198
199done:
200 /* reset to read mode */
201 *addr = BANK_CMD_RST;
202
203 return (retval);
204}
205
206/*-----------------------------------------------------------------------
207 */
208
209unsigned long
wdenkb00ec162003-06-19 23:40:20 +0000210flash_init (void)
wdenkaffae2b2002-08-17 09:36:01 +0000211{
212 int i;
213
214 /* Init: no FLASHes known */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200215 for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
wdenkaffae2b2002-08-17 09:36:01 +0000216 flash_info[i].flash_id = FLASH_UNKNOWN;
217 }
218
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219 bank_probe (&flash_info[0], (bank_addr_t)CONFIG_SYS_FLASH_BASE);
wdenkaffae2b2002-08-17 09:36:01 +0000220
221 /*
222 * protect monitor and environment sectors
223 */
224
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
wdenkb00ec162003-06-19 23:40:20 +0000226 (void)flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227 CONFIG_SYS_MONITOR_BASE,
228 CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
wdenkaffae2b2002-08-17 09:36:01 +0000229 &flash_info[0]);
230#endif
231
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232#if defined(CONFIG_SYS_FLASH_ENV_ADDR)
wdenkb00ec162003-06-19 23:40:20 +0000233 (void)flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200234 CONFIG_SYS_FLASH_ENV_ADDR,
235#if defined(CONFIG_SYS_FLASH_ENV_BUF)
236 CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_BUF - 1,
wdenkaffae2b2002-08-17 09:36:01 +0000237#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238 CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_SIZE - 1,
wdenkaffae2b2002-08-17 09:36:01 +0000239#endif
240 &flash_info[0]);
241#endif
242
243 return flash_info[0].size;
244}
245
246/*-----------------------------------------------------------------------
247 */
wdenkaffae2b2002-08-17 09:36:01 +0000248void
wdenkb00ec162003-06-19 23:40:20 +0000249flash_print_info (flash_info_t *info)
wdenkaffae2b2002-08-17 09:36:01 +0000250{
251 int i;
252
253 if (info->flash_id == FLASH_UNKNOWN) {
254 printf ("missing or unknown FLASH type\n");
255 return;
256 }
257
258 switch (info->flash_id & FLASH_VENDMASK) {
259 case FLASH_MAN_INTEL: printf ("INTEL "); break;
260 default: printf ("Unknown Vendor "); break;
261 }
262
263 switch (info->flash_id & FLASH_TYPEMASK) {
264 case FLASH_28F320J5: printf ("28F320J5 (32 Mbit, 2 x 16bit)\n");
265 break;
wdenkb00ec162003-06-19 23:40:20 +0000266 case FLASH_28F640J5: printf ("28F640J5 (64 Mbit, 2 x 16bit)\n");
267 break;
268 case FLASH_28F320J3A: printf ("28F320J3A (32 Mbit, 2 x 16bit)\n");
269 break;
270 case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 2 x 16bit)\n");
271 break;
272 case FLASH_28F128J3A: printf ("28F320J3A (128 Mbit, 2 x 16bit)\n");
273 break;
wdenkaffae2b2002-08-17 09:36:01 +0000274 default: printf ("Unknown Chip Type\n");
275 break;
276 }
277
278 printf (" Size: %ld MB in %d Sectors\n",
279 info->size >> 20, info->sector_count);
280
281 printf (" Sector Start Addresses:");
282 for (i=0; i<info->sector_count; ++i) {
283 if ((i % 5) == 0)
284 printf ("\n ");
285 printf (" %08lX%s",
286 info->start[i],
287 info->protect[i] ? " (RO)" : " "
288 );
289 }
290 printf ("\n");
291 return;
292}
293
wdenkaffae2b2002-08-17 09:36:01 +0000294/*
295 * The following code cannot be run from FLASH!
296 */
wdenkaffae2b2002-08-17 09:36:01 +0000297
298/*-----------------------------------------------------------------------
299 */
300
301int
wdenkb00ec162003-06-19 23:40:20 +0000302flash_erase (flash_info_t *info, int s_first, int s_last)
wdenkaffae2b2002-08-17 09:36:01 +0000303{
304 int prot, sect, haderr;
305 ulong start, now, last;
306 int rcode = 0;
307
308#ifdef FLASH_DEBUG
wdenkb00ec162003-06-19 23:40:20 +0000309 printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
wdenkaffae2b2002-08-17 09:36:01 +0000310 " Bank # %d: ", s_last - s_first + 1, s_first, s_last,
311 (info - flash_info) + 1);
wdenkb00ec162003-06-19 23:40:20 +0000312 flash_print_info (info);
wdenkaffae2b2002-08-17 09:36:01 +0000313#endif
314
315 if ((s_first < 0) || (s_first > s_last)) {
316 if (info->flash_id == FLASH_UNKNOWN) {
317 printf ("- missing\n");
318 } else {
319 printf ("- no sectors to erase\n");
320 }
321 return 1;
322 }
323
324 prot = 0;
wdenkb00ec162003-06-19 23:40:20 +0000325 for (sect = s_first; sect <= s_last; ++sect) {
wdenkaffae2b2002-08-17 09:36:01 +0000326 if (info->protect[sect]) {
327 prot++;
328 }
329 }
330
331 if (prot) {
wdenkb00ec162003-06-19 23:40:20 +0000332 printf ("- Warning: %d protected sector%s will not be erased\n",
wdenkaffae2b2002-08-17 09:36:01 +0000333 prot, (prot > 1 ? "s" : ""));
334 }
335
336 start = get_timer (0);
337 last = 0;
338 haderr = 0;
339
340 for (sect = s_first; sect <= s_last; sect++) {
341 if (info->protect[sect] == 0) { /* not protected */
342 ulong estart;
343 int sectdone;
344
wdenkb00ec162003-06-19 23:40:20 +0000345 bank_erase_init (info, sect);
wdenkaffae2b2002-08-17 09:36:01 +0000346
347 /* wait at least 80us - let's wait 1 ms */
348 udelay (1000);
349
wdenkb00ec162003-06-19 23:40:20 +0000350 estart = get_timer (start);
wdenkaffae2b2002-08-17 09:36:01 +0000351
352 do {
wdenkb00ec162003-06-19 23:40:20 +0000353 now = get_timer (start);
wdenkaffae2b2002-08-17 09:36:01 +0000354
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200355 if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
wdenkaffae2b2002-08-17 09:36:01 +0000356 printf ("Timeout (sect %d)\n", sect);
357 haderr = 1;
358 rcode = 1;
359 break;
360 }
361
362#ifndef FLASH_DEBUG
363 /* show that we're waiting */
364 if ((now - last) > 1000) { /* every second */
365 putc ('.');
366 last = now;
367 }
368#endif
369
wdenkb00ec162003-06-19 23:40:20 +0000370 sectdone = bank_erase_poll (info, sect);
wdenkaffae2b2002-08-17 09:36:01 +0000371
372 if (sectdone < 0) {
373 haderr = 1;
374 rcode = 1;
375 break;
376 }
377
378 } while (!sectdone);
379
380 if (haderr)
381 break;
382 }
383 }
384
385 if (haderr > 0)
386 printf (" failed\n");
387 else
388 printf (" done\n");
389
390 /* reset to read mode */
391 for (sect = s_first; sect <= s_last; sect++) {
392 if (info->protect[sect] == 0) { /* not protected */
wdenkb00ec162003-06-19 23:40:20 +0000393 bank_reset (info, sect);
wdenkaffae2b2002-08-17 09:36:01 +0000394 }
395 }
396 return rcode;
397}
398
399/*-----------------------------------------------------------------------
wdenkb00ec162003-06-19 23:40:20 +0000400 * Write a word to Flash, returns:
401 * 0 - OK
402 * 1 - write timeout
403 * 2 - Flash not erased
404 * 3 - Program failed
405 */
406static int
407write_word (flash_info_t *info, ulong dest, ulong data)
408{
409 /* Check if Flash is (sufficiently) erased */
410 if ((*(ulong *)dest & data) != data)
411 return (2);
412
413 return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data));
414}
415
416/*-----------------------------------------------------------------------
wdenkaffae2b2002-08-17 09:36:01 +0000417 * Copy memory to flash, returns:
418 * 0 - OK
419 * 1 - write timeout
420 * 2 - Flash not erased
wdenkb00ec162003-06-19 23:40:20 +0000421 * 3 - Program failed
wdenkaffae2b2002-08-17 09:36:01 +0000422 */
423
424int
wdenkb00ec162003-06-19 23:40:20 +0000425write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
wdenkaffae2b2002-08-17 09:36:01 +0000426{
427 ulong cp, wp, data;
428 int i, l, rc;
429
430 wp = (addr & ~3); /* get lower word aligned address */
431
432 /*
433 * handle unaligned start bytes
434 */
435 if ((l = addr - wp) != 0) {
436 data = 0;
437 for (i=0, cp=wp; i<l; ++i, ++cp) {
438 data = (data << 8) | (*(uchar *)cp);
439 }
440 for (; i<4 && cnt>0; ++i) {
441 data = (data << 8) | *src++;
442 --cnt;
443 ++cp;
444 }
445 for (; cnt==0 && i<4; ++i, ++cp) {
446 data = (data << 8) | (*(uchar *)cp);
447 }
448
wdenkb00ec162003-06-19 23:40:20 +0000449 if ((rc = write_word (info, wp, data)) != 0) {
wdenkaffae2b2002-08-17 09:36:01 +0000450 return (rc);
451 }
452 wp += 4;
453 }
454
455 /*
456 * handle word aligned part
457 */
458 while (cnt >= 4) {
459 data = 0;
460 for (i=0; i<4; ++i) {
461 data = (data << 8) | *src++;
462 }
wdenkb00ec162003-06-19 23:40:20 +0000463 if ((rc = write_word (info, wp, data)) != 0) {
wdenkaffae2b2002-08-17 09:36:01 +0000464 return (rc);
465 }
466 wp += 4;
467 cnt -= 4;
468 }
469
470 if (cnt == 0) {
471 return (0);
472 }
473
474 /*
475 * handle unaligned tail bytes
476 */
477 data = 0;
478 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
479 data = (data << 8) | *src++;
480 --cnt;
481 }
482 for (; i<4; ++i, ++cp) {
483 data = (data << 8) | (*(uchar *)cp);
484 }
485
wdenkb00ec162003-06-19 23:40:20 +0000486 return (write_word (info, wp, data));
wdenkaffae2b2002-08-17 09:36:01 +0000487}
488
489/*-----------------------------------------------------------------------
490 */