| Georg Schardt | 3ce59a1 | 2008-10-24 13:51:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * |
| 4 | * Georg Schardt <schardt@team-ctech.de> |
| 5 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| Georg Schardt | 3ce59a1 | 2008-10-24 13:51:52 +0200 | [diff] [blame] | 7 | * |
| 8 | * CAUTION: This file is based on the xparameters.h automatically |
| 9 | * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5 |
| 10 | */ |
| 11 | |
| 12 | #ifndef __XPARAMETER_H__ |
| 13 | #define __XPARAMETER_H__ |
| 14 | |
| 15 | /* RS232 */ |
| 16 | #define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 |
| 17 | #define XPAR_UARTNS550_0_BASEADDR 0x83E00000 |
| 18 | |
| 19 | |
| 20 | /* INT_C */ |
| 21 | #define XPAR_XPS_INTC_0_DEVICE_ID 0 |
| 22 | #define XPAR_XPS_INTC_0_BASEADDR 0x81800000 |
| 23 | #define XPAR_INTC_MAX_NUM_INTR_INPUTS 2 |
| 24 | |
| 25 | /* CPU core clock */ |
| 26 | #define XPAR_CORE_CLOCK_FREQ_HZ 300000000 |
| 27 | #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 |
| 28 | |
| 29 | /* RAM */ |
| 30 | #define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 |
| 31 | |
| 32 | /* FLASH */ |
| Ricardo Ribalda Delgado | 63d0ac9 | 2008-10-27 12:35:59 +0100 | [diff] [blame] | 33 | #define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000 |
| Georg Schardt | 3ce59a1 | 2008-10-24 13:51:52 +0200 | [diff] [blame] | 34 | |
| 35 | #endif |