| Roy Spliet | 6a99b33 | 2015-05-26 17:00:40 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef _SUNXI_DMA_SUN4I_H |
| 8 | #define _SUNXI_DMA_SUN4I_H |
| 9 | |
| 10 | struct sunxi_dma_cfg |
| 11 | { |
| 12 | u32 ctl; /* 0x00 Control */ |
| 13 | u32 src_addr; /* 0x04 Source address */ |
| 14 | u32 dst_addr; /* 0x08 Destination address */ |
| 15 | u32 bc; /* 0x0C Byte counter */ |
| 16 | u32 res0[2]; |
| 17 | u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */ |
| 18 | u32 res1; |
| 19 | }; |
| 20 | |
| 21 | struct sunxi_dma |
| 22 | { |
| 23 | u32 irq_en; /* 0x000 IRQ enable */ |
| 24 | u32 irq_pend; /* 0x004 IRQ pending */ |
| 25 | u32 auto_gate; /* 0x008 auto gating */ |
| 26 | u32 res0[61]; |
| 27 | struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */ |
| 28 | u32 res1[64]; |
| 29 | struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */ |
| 30 | }; |
| 31 | |
| 32 | enum ddma_drq_type { |
| 33 | DDMA_DST_DRQ_SRAM = 0, |
| 34 | DDMA_SRC_DRQ_SRAM = 0, |
| 35 | DDMA_DST_DRQ_SDRAM = 1, |
| 36 | DDMA_SRC_DRQ_SDRAM = 1, |
| 37 | DDMA_DST_DRQ_PATA = 2, |
| 38 | DDMA_SRC_DRQ_PATA = 2, |
| 39 | DDMA_DST_DRQ_NAND = 3, |
| 40 | DDMA_SRC_DRQ_NAND = 3, |
| 41 | DDMA_DST_DRQ_USB0 = 4, |
| 42 | DDMA_SRC_DRQ_USB0 = 4, |
| 43 | DDMA_DST_DRQ_ETHERNET_MAC_TX = 6, |
| 44 | DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7, |
| 45 | DDMA_DST_DRQ_SPI1_TX = 8, |
| 46 | DDMA_SRC_DRQ_SPI1_RX = 9, |
| 47 | DDMA_DST_DRQ_SECURITY_SYS_TX = 10, |
| 48 | DDMA_SRC_DRQ_SECURITY_SYS_RX = 11, |
| 49 | DDMA_DST_DRQ_TCON0 = 14, |
| 50 | DDMA_DST_DRQ_TCON1 = 15, |
| 51 | DDMA_DST_DRQ_MSC = 23, |
| 52 | DDMA_SRC_DRQ_MSC = 23, |
| 53 | DDMA_DST_DRQ_SPI0_TX = 26, |
| 54 | DDMA_SRC_DRQ_SPI0_RX = 27, |
| 55 | DDMA_DST_DRQ_SPI2_TX = 28, |
| 56 | DDMA_SRC_DRQ_SPI2_RX = 29, |
| 57 | DDMA_DST_DRQ_SPI3_TX = 30, |
| 58 | DDMA_SRC_DRQ_SPI3_RX = 31, |
| 59 | }; |
| 60 | |
| 61 | #define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) & 0x1f) |
| 62 | #define SUNXI_DMA_CTL_MODE_IO (1 << 5) |
| 63 | #define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 (2 << 9) |
| 64 | #define SUNXI_DMA_CTL_DST_DRQ(a) (((a) & 0x1f) << 16) |
| 65 | #define SUNXI_DMA_CTL_DST_DATA_WIDTH_32 (2 << 25) |
| 66 | #define SUNXI_DMA_CTL_TRIGGER (1 << 31) |
| 67 | |
| 68 | #endif /* _SUNXI_DMA_SUN4I_H */ |