blob: 2267677d2eb93300d52007ccce06c92af3dbf776 [file] [log] [blame]
wdenk265d2172004-07-10 22:35:59 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Configuration settings for the sbc8240 board.
26 */
27
28/* ------------------------------------------------------------------------- */
29
30/*
31 * board/config.h - configuration options, board specific
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41
42#define CONFIG_MPC824X 1
43#define CONFIG_MPC8240 1
44#define CONFIG_WRSBC8240 1
45
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020046#define CONFIG_SYS_TEXT_BASE 0xFFF00000
47
wdenk265d2172004-07-10 22:35:59 +000048#define CONFIG_CONS_INDEX 1
49#define CONFIG_BAUDRATE 9600
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk265d2172004-07-10 22:35:59 +000051
52#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo"
53
54#undef CONFIG_BOOTARGS
55
56#define CONFIG_BOOTCOMMAND "version;echo;tftpboot $loadaddr $loadfile;bootvx" /* autoboot command */
57
58#define CONFIG_EXTRA_ENV_SETTINGS \
59 "bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \
60 "e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \
61 "tn=sbc8240 o=fei \0" \
62 "env_startaddr=FFF70000\0" \
63 "env_endaddr=FFF7FFFF\0" \
64 "loadfile=vxWorks.st\0" \
65 "loadaddr=0x01000000\0" \
66 "net_load=tftpboot $loadaddr $loadfile\0" \
67 "uboot_startaddr=FFF00000\0" \
68 "uboot_endaddr=FFF3FFFF\0" \
69 "update=tftp $loadaddr /u-boot.bin;" \
70 "protect off $uboot_startaddr $uboot_endaddr;" \
71 "era $uboot_startaddr $uboot_endaddr;" \
72 "cp.b $loadaddr $uboot_startaddr $filesize;" \
73 "protect on $uboot_startaddr $uboot_endaddr\0" \
74 "zapenv=protect off $env_startaddr $env_endaddr;" \
75 "era $env_startaddr $env_endaddr;" \
76 "protect on $env_startaddr $env_endaddr\0"
77
78#define CONFIG_BOOTDELAY 5
79
Jon Loeligerc6d535a2007-07-09 21:57:31 -050080/*
81 * BOOTP options
82 */
83#define CONFIG_BOOTP_SUBNETMASK
84#define CONFIG_BOOTP_GATEWAY
85#define CONFIG_BOOTP_HOSTNAME
86#define CONFIG_BOOTP_BOOTPATH
87#define CONFIG_BOOTP_BOOTFILESIZE
88
wdenk265d2172004-07-10 22:35:59 +000089
90#define CONFIG_ENV_OVERWRITE
91
wdenk265d2172004-07-10 22:35:59 +000092
Jon Loeliger1f166a22007-07-04 22:30:58 -050093/*
94 * Command line configuration.
wdenk265d2172004-07-10 22:35:59 +000095 */
Jon Loeliger1f166a22007-07-04 22:30:58 -050096#include <config_cmd_default.h>
97
98#define CONFIG_CMD_BSP
99#define CONFIG_CMD_DIAG
100#define CONFIG_CMD_ELF
Mike Frysinger78dcaf42009-01-28 19:08:14 -0500101#define CONFIG_CMD_SAVEENV
Jon Loeliger1f166a22007-07-04 22:30:58 -0500102#define CONFIG_CMD_FLASH
103#define CONFIG_CMD_PCI
104#define CONFIG_CMD_PING
105#define CONFIG_CMD_SDRAM
106
wdenk265d2172004-07-10 22:35:59 +0000107
108/*
109 * Miscellaneous configurable options
110 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#define CONFIG_SYS_LONGHELP /* undef to save memory */
112#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
113#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk265d2172004-07-10 22:35:59 +0000114
115#if 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
wdenk265d2172004-07-10 22:35:59 +0000117#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200118#ifdef CONFIG_SYS_HUSH_PARSER
119#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk265d2172004-07-10 22:35:59 +0000120#endif
121
122#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
123#define CONFIG_IPADDR 192.168.193.102
124#define CONFIG_NETMASK 255.255.255.248
125#define CONFIG_SERVERIP 192.168.193.99
126
127#define CONFIG_STATUS_LED /* Status LED enabled */
128#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
129
130#define STATUS_LED_BIT 0x00000001
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
wdenk265d2172004-07-10 22:35:59 +0000132#define STATUS_LED_STATE STATUS_LED_BLINKING
133#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
134#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
135
136#ifndef __ASSEMBLY__
137/* LEDs */
138typedef unsigned int led_id_t;
139
140#define __led_toggle(_msk) \
141 do { \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142 *((volatile char *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
wdenk265d2172004-07-10 22:35:59 +0000143 } while(0)
144
145#define __led_set(_msk, _st) \
146 do { \
147 if ((_st)) \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148 *((volatile char *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
wdenk265d2172004-07-10 22:35:59 +0000149 else \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150 *((volatile char *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
wdenk265d2172004-07-10 22:35:59 +0000151 } while(0)
152
153#define __led_init(msk, st) __led_set(msk, st)
154
155#endif
156
157#define CONFIG_MISC_INIT_R
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_LED_BASE 0xFFE80000
wdenk265d2172004-07-10 22:35:59 +0000159
160/* Print Buffer Size
161 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200162#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenk265d2172004-07-10 22:35:59 +0000163
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
165#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
166#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenk265d2172004-07-10 22:35:59 +0000167
168/*-----------------------------------------------------------------------
169 * Start addresses for the final memory configuration
170 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk265d2172004-07-10 22:35:59 +0000172 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_SDRAM_BASE 0x00000000
174#define CONFIG_SYS_FLASH_BASE 0xFFF00000
wdenk265d2172004-07-10 22:35:59 +0000175
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenk265d2172004-07-10 22:35:59 +0000177
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
wdenk265d2172004-07-10 22:35:59 +0000179
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200180#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenk265d2172004-07-10 22:35:59 +0000181
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
183#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk265d2172004-07-10 22:35:59 +0000184
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
186#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenk265d2172004-07-10 22:35:59 +0000187
188 /* Maximum amount of RAM.
189 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
wdenk265d2172004-07-10 22:35:59 +0000191
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
193#undef CONFIG_SYS_RAMBOOT
wdenk265d2172004-07-10 22:35:59 +0000194#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_RAMBOOT
wdenk265d2172004-07-10 22:35:59 +0000196#endif
197
198/*-----------------------------------------------------------------------
199 * Definitions for initial stack pointer and data area
200 */
201
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200203#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk0191e472010-10-26 14:34:52 +0200204#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk265d2172004-07-10 22:35:59 +0000205
206/*
207 * NS16550 Configuration
208 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_NS16550
210#define CONFIG_SYS_NS16550_SERIAL
wdenk265d2172004-07-10 22:35:59 +0000211
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk265d2172004-07-10 22:35:59 +0000213
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_NS16550_CLK 3686400
wdenk265d2172004-07-10 22:35:59 +0000215
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_NS16550_COM1 0xFFF80000
wdenk265d2172004-07-10 22:35:59 +0000217
218/*
219 * Low Level Configuration Settings
220 * (address mappings, register initial values, etc.)
221 * You should know what you are doing if you make changes here.
222 * For the detail description refer to the MPC8240 user's manual.
223 */
224
225#define CONFIG_SYS_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_HZ 1000
wdenk265d2172004-07-10 22:35:59 +0000227#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
228
229 /* Bit-field values for MCCR1.
230 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_ROMNAL 0
232#define CONFIG_SYS_ROMFAL 7
wdenk265d2172004-07-10 22:35:59 +0000233
234 /* Bit-field values for MCCR2.
235 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_REFINT 430 /* Refresh interval */
wdenk265d2172004-07-10 22:35:59 +0000237
238 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
239 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#define CONFIG_SYS_BSTOPRE 192
wdenk265d2172004-07-10 22:35:59 +0000241
242 /* Bit-field values for MCCR3.
243 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200244#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
245#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
wdenk265d2172004-07-10 22:35:59 +0000246
247 /* Bit-field values for MCCR4.
248 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200249#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
250#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
251#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
252#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
253#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
254#define CONFIG_SYS_ACTORW 2
255#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
wdenk265d2172004-07-10 22:35:59 +0000256
257/* Memory bank settings.
258 * Only bits 20-29 are actually used from these vales to set the
259 * start/end addresses. The upper two bits will always be 0, and the lower
260 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
261 * address. Refer to the MPC8240 book.
262 */
263
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264#define CONFIG_SYS_BANK0_START 0x00000000
265#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
266#define CONFIG_SYS_BANK0_ENABLE 1
267#define CONFIG_SYS_BANK1_START 0x3ff00000
268#define CONFIG_SYS_BANK1_END 0x3fffffff
269#define CONFIG_SYS_BANK1_ENABLE 0
270#define CONFIG_SYS_BANK2_START 0x3ff00000
271#define CONFIG_SYS_BANK2_END 0x3fffffff
272#define CONFIG_SYS_BANK2_ENABLE 0
273#define CONFIG_SYS_BANK3_START 0x3ff00000
274#define CONFIG_SYS_BANK3_END 0x3fffffff
275#define CONFIG_SYS_BANK3_ENABLE 0
276#define CONFIG_SYS_BANK4_START 0x3ff00000
277#define CONFIG_SYS_BANK4_END 0x3fffffff
278#define CONFIG_SYS_BANK4_ENABLE 0
279#define CONFIG_SYS_BANK5_START 0x3ff00000
280#define CONFIG_SYS_BANK5_END 0x3fffffff
281#define CONFIG_SYS_BANK5_ENABLE 0
282#define CONFIG_SYS_BANK6_START 0x3ff00000
283#define CONFIG_SYS_BANK6_END 0x3fffffff
284#define CONFIG_SYS_BANK6_ENABLE 0
285#define CONFIG_SYS_BANK7_START 0x3ff00000
286#define CONFIG_SYS_BANK7_END 0x3fffffff
287#define CONFIG_SYS_BANK7_ENABLE 0
wdenk265d2172004-07-10 22:35:59 +0000288
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200289#define CONFIG_SYS_ODCR 0xff
wdenk265d2172004-07-10 22:35:59 +0000290
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200291#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
292#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk265d2172004-07-10 22:35:59 +0000293
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200294#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
295#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenk265d2172004-07-10 22:35:59 +0000296
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200297#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
298#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk265d2172004-07-10 22:35:59 +0000299
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200300#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
301#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
wdenk265d2172004-07-10 22:35:59 +0000302
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
304#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
305#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
306#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
307#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
308#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
309#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
310#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenk265d2172004-07-10 22:35:59 +0000311
312/*
313 * For booting Linux, the board info and command line data
314 * have to be in the first 8 MB of memory, since this is
315 * the maximum mapped by the Linux kernel during initialization.
316 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk265d2172004-07-10 22:35:59 +0000318
319/*-----------------------------------------------------------------------
320 * FLASH organization
321 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200322#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
323#define CONFIG_SYS_MAX_FLASH_SECT 256 /* Max number of sectors in one bank */
wdenk265d2172004-07-10 22:35:59 +0000324
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200325#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
326#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk265d2172004-07-10 22:35:59 +0000327
328/*
329 * Init Memory Controller:
330 *
331 * BR0/1 and OR0/1 (FLASH)
332 */
333
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200334#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
wdenk265d2172004-07-10 22:35:59 +0000335#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
336
337 /* Warining: environment is not EMBEDDED in the U-Boot code.
338 * It's stored in flash separately.
339 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200340#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200341#define CONFIG_ENV_ADDR 0xFFF70000
342#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
343#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
344#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
wdenk265d2172004-07-10 22:35:59 +0000345
346/*-----------------------------------------------------------------------
347 * Cache Configuration
348 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200349#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger1f166a22007-07-04 22:30:58 -0500350#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200351# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk265d2172004-07-10 22:35:59 +0000352#endif
353
wdenk265d2172004-07-10 22:35:59 +0000354/*-----------------------------------------------------------------------
355 * PCI stuff
356 *-----------------------------------------------------------------------
357 */
358#define CONFIG_PCI /* include pci support */
359#define CONFIG_PCI_PNP /* we need Plug 'n Play */
360#define CONFIG_NET_MULTI /* Multi ethernet cards support */
361#define CONFIG_TULIP
362#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200363#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk265d2172004-07-10 22:35:59 +0000364#endif /* __CONFIG_H */