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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Anatolij Gustschin705bf372016-11-14 16:07:10 +01002/*
3 * Copyright Altera Corporation (C) 2015
Anatolij Gustschin705bf372016-11-14 16:07:10 +01004 */
5
6#include "socfpga_cyclone5.dtsi"
Simon Goldschmidt64a12bf2019-03-01 20:12:29 +01007#include "socfpga-common-u-boot.dtsi"
Anatolij Gustschin705bf372016-11-14 16:07:10 +01008
9/ {
10 model = "Terasic DE1-SoC";
11 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
12
13 chosen {
14 bootargs = "console=ttyS0,115200";
Simon Goldschmidt3854a1a2018-08-13 21:34:33 +020015 stdout-path = "serial0:115200n8";
Anatolij Gustschin705bf372016-11-14 16:07:10 +010016 };
17
18 aliases {
19 ethernet0 = &gmac1;
20 udc0 = &usb1;
21 };
22
23 memory {
24 name = "memory";
25 device_type = "memory";
26 reg = <0x0 0x40000000>; /* 1GB */
27 };
Anatolij Gustschin705bf372016-11-14 16:07:10 +010028};
29
30&gmac1 {
31 status = "okay";
32 phy-mode = "rgmii";
33
34 rxd0-skew-ps = <420>;
35 rxd1-skew-ps = <420>;
36 rxd2-skew-ps = <420>;
37 rxd3-skew-ps = <420>;
38 txen-skew-ps = <0>;
39 txc-skew-ps = <1860>;
40 rxdv-skew-ps = <420>;
41 rxc-skew-ps = <1680>;
42};
43
44&gpio0 {
45 status = "okay";
46};
47
48&gpio1 {
49 status = "okay";
50};
51
52&gpio2 {
53 status = "okay";
54};
55
Simon Goldschmidt15616b52018-11-02 11:54:52 +010056&porta {
57 bank-name = "porta";
58};
59
60&portb {
61 bank-name = "portb";
62};
63
64&portc {
65 bank-name = "portc";
66};
67
Anatolij Gustschin705bf372016-11-14 16:07:10 +010068&mmc0 {
69 status = "okay";
70 u-boot,dm-pre-reloc;
71};
72
73&usb1 {
74 status = "okay";
75};
Simon Goldschmidt3854a1a2018-08-13 21:34:33 +020076
77&uart0 {
Jade Lovelace6fcc9872023-02-10 17:15:26 -080078 clock-frequency = <100000000>;
Simon Goldschmidt3854a1a2018-08-13 21:34:33 +020079 u-boot,dm-pre-reloc;
80};
Simon Goldschmidt15616b52018-11-02 11:54:52 +010081
82&watchdog0 {
83 status = "disabled";
84};