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git01.mediatek.com / filogic / uboot / c9c953999b6d4f728a1e9d5a9a3568925c78ef9b / . / arch / arm / dts / sdm845.dtsi
blob: 607af277f8be9e5aa12d37973727210555fb4dd1 [file] [log] [blame]
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Qualcomm SDM845 chip device tree source
4 *
5 * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
6 *
7 */
8
9/dts-v1/;
10
Sumit Garg8bdffc32022-07-12 12:42:06 +0530[diff] [blame]11#include <dt-bindings/clock/qcom,gcc-sdm845.h>
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]12#include "skeleton64.dtsi"
13
14/ {
15 soc: soc {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges = <0 0 0 0xffffffff>;
19 compatible = "simple-bus";
20
21 gcc: clock-controller@100000 {
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]22 compatible = "qcom,gcc-sdm845";
23 reg = <0x100000 0x1f0000>;
24 #clock-cells = <1>;
25 #reset-cells = <1>;
26 #power-domain-cells = <1>;
27 };
28
29 gpio_north: gpio_north@3900000 {
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]30 #gpio-cells = <2>;
31 compatible = "qcom,sdm845-pinctrl";
32 reg = <0x3900000 0x400000>;
33 gpio-count = <150>;
34 gpio-controller;
35 gpio-ranges = <&gpio_north 0 0 150>;
36 gpio-bank-name = "soc_north.";
37 };
38
39 tlmm_north: pinctrl_north@3900000 {
Sumit Gargb7572e52022-07-27 13:52:04 +0530[diff] [blame]40 compatible = "qcom,sdm845-pinctrl";
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]41 reg = <0x3900000 0x400000>;
42 gpio-count = <150>;
43 gpio-controller;
44 #gpio-cells = <2>;
45 gpio-ranges = <&tlmm_north 0 0 150>;
46
47 /* DEBUG UART */
48 qup_uart9: qup-uart9-default {
Dzmitry Sankouski8e3bdd52022-02-22 21:49:53 +0300[diff] [blame]49 pins = "GPIO_4", "GPIO_5";
Sumit Garg60b78042022-07-12 12:42:07 +0530[diff] [blame]50 function = "qup9";
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]51 };
52 };
53
54 debug_uart: serial@a84000 {
55 compatible = "qcom,msm-geni-uart";
56 reg = <0xa84000 0x4000>;
57 reg-names = "se_phys";
58 clock-names = "se-clk";
Sumit Garg8bdffc32022-07-12 12:42:06 +0530[diff] [blame]59 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
Dzmitry Sankouski2826cbd2021-10-17 13:44:31 +0300[diff] [blame]60 pinctrl-names = "default";
61 pinctrl-0 = <&qup_uart9>;
62 qcom,wrapper-core = <0x8a>;
63 status = "disabled";
64 };
65
66 spmi@c440000 {
67 compatible = "qcom,spmi-pmic-arb";
68 reg = <0xc440000 0x1100>,
69 <0xc600000 0x2000000>,
70 <0xe600000 0x100000>;
71 reg-names = "cnfg", "core", "obsrvr";
72 #address-cells = <0x1>;
73 #size-cells = <0x1>;
74
75 qcom,revid@100 {
76 compatible = "qcom,qpnp-revid";
77 reg = <0x100 0x100>;
78 };
79
80 pmic0: pm8998@0 {
81 compatible = "qcom,spmi-pmic";
82 reg = <0x0 0x1>;
83 #address-cells = <0x1>;
84 #size-cells = <0x1>;
85
86 pm8998_pon: pm8998_pon@800 {
87 compatible = "qcom,pm8998-pwrkey";
88 reg = <0x800 0x100>;
89 #gpio-cells = <2>;
90 gpio-controller;
91 gpio-bank-name = "pm8998_key.";
92 };
93
94 pm8998_gpios: pm8998_gpios@c000 {
95 compatible = "qcom,pm8998-gpio";
96 reg = <0xc000 0x1a00>;
97 gpio-controller;
98 gpio-count = <21>;
99 #gpio-cells = <2>;
100 gpio-bank-name = "pm8998.";
101 };
102 };
103
104 pmic1: pm8998@1 {
105 compatible = "qcom,spmi-pmic";
106 reg = <0x1 0x0>;
107 #address-cells = <0x2>;
108 #size-cells = <0x0>;
109 };
110 };
111 };
112};