Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / c9c953999b6d4f728a1e9d5a9a3568925c78ef9b / . / arch / arm / dts / imx8mp-dhcom-som.dtsi
blob: 0f13ee36277151479f98e3ed3b31531620888856 [file] [log] [blame]
Marcel Ziswilercdfde792022-11-07 22:22:39 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasutf670cd72022-05-21 16:56:26 +0200[diff] [blame]2/*
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mp.dtsi"
7
8/ {
9 model = "DH electronics i.MX8M Plus DHCOM SoM";
10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
11
12 aliases {
13 ethernet0 = &eqos;
14 ethernet1 = &fec;
15 rtc0 = &rv3032;
16 rtc1 = &snvs_rtc;
17 spi0 = &flexspi;
18 };
19
20 memory@40000000 {
21 device_type = "memory";
22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
23 reg = <0x0 0x40000000 0 0x08000000>;
24 };
25
26 reg_eth_vio: regulator-eth-vio {
27 compatible = "regulator-fixed";
28 gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
29 pinctrl-0 = <&pinctrl_enet_vio>;
30 pinctrl-names = "default";
31 regulator-always-on;
32 regulator-boot-on;
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-name = "eth_vio";
36 vin-supply = <&buck4>;
37 };
38
39 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
40 compatible = "regulator-fixed";
41 enable-active-high;
42 gpio = <&gpio2 19 0>; /* SD2_RESET */
43 off-on-delay-us = <12000>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
46 regulator-max-microvolt = <3300000>;
47 regulator-min-microvolt = <3300000>;
48 regulator-name = "VDD_3V3_SD";
49 startup-delay-us = <100>;
50 vin-supply = <&buck4>;
51 };
52};
53
54&A53_0 {
55 cpu-supply = <&buck2>;
56};
57
58&A53_1 {
59 cpu-supply = <&buck2>;
60};
61
62&A53_2 {
63 cpu-supply = <&buck2>;
64};
65
66&A53_3 {
67 cpu-supply = <&buck2>;
68};
69
70&ecspi1 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_ecspi1>;
Marek Vasuteee69bd2022-08-12 22:41:54 +0200[diff] [blame]73 cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
Marek Vasutf670cd72022-05-21 16:56:26 +0200[diff] [blame]74 status = "disabled";
75};
76
77&ecspi2 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_ecspi2>;
80 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
81 status = "disabled";
82};
83
84&eqos { /* First ethernet */
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_eqos>;
87 phy-handle = <&ethphy0g>;
88 phy-mode = "rgmii-id";
89 status = "okay";
90
91 mdio {
92 compatible = "snps,dwmac-mdio";
93 #address-cells = <1>;
94 #size-cells = <0>;
95
96 /* Up to one of these two PHYs may be populated. */
97 ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
98 compatible = "ethernet-phy-id0007.c110",
99 "ethernet-phy-ieee802.3-c22";
100 interrupt-parent = <&gpio3>;
101 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
102 pinctrl-0 = <&pinctrl_ethphy0>;
103 pinctrl-names = "default";
104 reg = <1>;
105 reset-assert-us = <1000>;
106 reset-deassert-us = <1000>;
107 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
108 /* Non-default PHY population option. */
109 status = "disabled";
110 };
111
112 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
113 compatible = "ethernet-phy-id0022.1642",
114 "ethernet-phy-ieee802.3-c22";
115 interrupt-parent = <&gpio3>;
116 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
117 micrel,led-mode = <0>;
118 pinctrl-0 = <&pinctrl_ethphy0>;
119 pinctrl-names = "default";
120 reg = <5>;
121 reset-assert-us = <1000>;
122 reset-deassert-us = <1000>;
123 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
124 /* Default PHY population option. */
125 status = "okay";
126 };
127 };
128};
129
130&fec { /* Second ethernet */
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_fec>;
133 phy-handle = <&ethphy1f>;
134 phy-mode = "rgmii";
135 fsl,magic-packet;
136 status = "okay";
137
138 mdio {
139 #address-cells = <1>;
140 #size-cells = <0>;
141
142 /* Up to one PHY may be populated. */
143 ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
144 compatible = "ethernet-phy-id0007.c110",
145 "ethernet-phy-ieee802.3-c22";
146 interrupt-parent = <&gpio4>;
147 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
148 pinctrl-0 = <&pinctrl_ethphy1>;
149 pinctrl-names = "default";
150 reg = <1>;
151 reset-assert-us = <1000>;
152 reset-deassert-us = <1000>;
153 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
154 /* Non-default PHY population option. */
155 status = "disabled";
156 };
157 };
158};
159
160&flexcan1 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_flexcan1>;
163 status = "disabled";
164};
165
166&flexcan2 {
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_flexcan2>;
169 status = "disabled";
170};
171
172&flexspi {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_flexspi>;
175 status = "okay";
176
177 flash@0 { /* W25Q128JWPIM */
178 compatible = "jedec,spi-nor";
179 reg = <0>;
180 spi-max-frequency = <80000000>;
181 spi-tx-bus-width = <4>;
182 spi-rx-bus-width = <4>;
183 };
184};
185
186&gpio1 {
187 gpio-line-names =
188 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
189 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
190 "", "", "", "", "", "", "", "",
191 "", "", "", "", "", "", "", "";
192};
193
194&gpio2 {
195 gpio-line-names =
196 "", "", "", "", "", "", "", "",
197 "", "", "", "DHCOM-K", "", "", "", "",
198 "", "", "", "", "DHCOM-INT", "", "", "",
199 "", "", "", "", "", "", "", "";
200};
201
202&gpio3 {
203 gpio-line-names =
204 "", "", "", "", "", "", "", "",
205 "", "", "", "", "", "", "SOM-HW0", "",
206 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
207 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
208};
209
210&gpio4 {
211 gpio-line-names =
212 "", "", "", "", "", "", "", "",
213 "", "", "", "", "", "", "", "",
214 "", "", "", "SOM-HW1", "", "", "", "",
215 "", "", "", "DHCOM-D", "", "", "", "";
216};
217
218&gpio5 {
219 gpio-line-names =
220 "", "", "DHCOM-C", "", "", "", "", "",
221 "", "", "", "", "", "", "", "",
222 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
223 "", "", "", "", "", "", "", "";
224};
225
226&i2c3 {
Marek Vasutf670cd72022-05-21 16:56:26 +0200[diff] [blame]227 clock-frequency = <100000>;
228 pinctrl-names = "default", "gpio";
229 pinctrl-0 = <&pinctrl_i2c3>;
230 pinctrl-1 = <&pinctrl_i2c3_gpio>;
231 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
232 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
233 status = "okay";
234
235 pmic: pmic@25 {
236 compatible = "nxp,pca9450c";
237 reg = <0x25>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_pmic>;
240 interrupt-parent = <&gpio1>;
241 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
242 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
243
244 /*
245 * i.MX 8M Plus Data Sheet for Consumer Products
246 * 3.1.4 Operating ranges
247 * MIMX8ML8CVNKZAB
248 */
249 regulators {
250 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
251 regulator-compatible = "BUCK1";
252 regulator-min-microvolt = <850000>;
253 regulator-max-microvolt = <1000000>;
254 regulator-ramp-delay = <3125>;
255 regulator-always-on;
256 regulator-boot-on;
257 };
258
259 buck2: BUCK2 { /* VDD_ARM */
260 regulator-compatible = "BUCK2";
261 regulator-min-microvolt = <850000>;
262 regulator-max-microvolt = <1000000>;
263 regulator-ramp-delay = <3125>;
264 regulator-always-on;
265 regulator-boot-on;
266 };
267
268 buck4: BUCK4 { /* VDD_3V3 */
269 regulator-compatible = "BUCK4";
270 regulator-min-microvolt = <3300000>;
271 regulator-max-microvolt = <3300000>;
272 regulator-always-on;
273 regulator-boot-on;
274 };
275
276 buck5: BUCK5 { /* VDD_1V8 */
277 regulator-compatible = "BUCK5";
278 regulator-min-microvolt = <1800000>;
279 regulator-max-microvolt = <1800000>;
280 regulator-always-on;
281 regulator-boot-on;
282 };
283
284 buck6: BUCK6 { /* NVCC_DRAM_1V1 */
285 regulator-compatible = "BUCK6";
286 regulator-min-microvolt = <1100000>;
287 regulator-max-microvolt = <1100000>;
288 regulator-always-on;
289 regulator-boot-on;
290 };
291
292 ldo1: LDO1 { /* NVCC_SNVS_1V8 */
293 regulator-compatible = "LDO1";
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <1800000>;
296 regulator-always-on;
297 regulator-boot-on;
298 };
299
300 ldo3: LDO3 { /* VDDA_1V8 */
301 regulator-compatible = "LDO3";
302 regulator-min-microvolt = <1800000>;
303 regulator-max-microvolt = <1800000>;
304 regulator-always-on;
305 regulator-boot-on;
306 };
307
308 ldo4: LDO4 { /* PMIC_LDO4 */
309 regulator-compatible = "LDO4";
310 regulator-min-microvolt = <3300000>;
311 regulator-max-microvolt = <3300000>;
312 };
313
314 ldo5: LDO5 { /* NVCC_SD2 */
315 regulator-compatible = "LDO5";
316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <3300000>;
318 };
319 };
320 };
321
322 adc@48 {
323 compatible = "ti,tla2024";
324 reg = <0x48>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327
328 channel@0 { /* Voltage over AIN0 and AIN1. */
329 reg = <0>;
330 };
331
332 channel@1 { /* Voltage over AIN0 and AIN3. */
333 reg = <1>;
334 };
335
336 channel@2 { /* Voltage over AIN1 and AIN3. */
337 reg = <2>;
338 };
339
340 channel@3 { /* Voltage over AIN2 and AIN3. */
341 reg = <3>;
342 };
343
344 channel@4 { /* Voltage over AIN0 and GND. */
345 reg = <4>;
346 };
347
348 channel@5 { /* Voltage over AIN1 and GND. */
349 reg = <5>;
350 };
351
352 channel@6 { /* Voltage over AIN2 and GND. */
353 reg = <6>;
354 };
355
356 channel@7 { /* Voltage over AIN3 and GND. */
357 reg = <7>;
358 };
359 };
360
361 touchscreen@49 {
362 compatible = "ti,tsc2004";
363 reg = <0x49>;
364 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_touch>;
367 vio-supply = <&buck4>;
368 };
369
370 eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */
371 compatible = "atmel,24c02";
372 pagesize = <16>;
373 reg = <0x50>;
374 };
375
376 rv3032: rtc@51 {
377 compatible = "microcrystal,rv3032";
378 reg = <0x51>;
379 interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_rtc>;
382 };
383
384 eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */
385 compatible = "atmel,24c02";
386 pagesize = <16>;
387 reg = <0x53>;
388 };
389};
390
391&i2c4 {
Marek Vasutf670cd72022-05-21 16:56:26 +0200[diff] [blame]392 clock-frequency = <100000>;
393 pinctrl-names = "default", "gpio";
394 pinctrl-0 = <&pinctrl_i2c4>;
395 pinctrl-1 = <&pinctrl_i2c4_gpio>;
396 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
397 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
398 status = "okay";
399};
400
401&i2c5 { /* HDMI EDID bus */
Marek Vasutf670cd72022-05-21 16:56:26 +0200[diff] [blame]402 clock-frequency = <100000>;
403 pinctrl-names = "default", "gpio";
404 pinctrl-0 = <&pinctrl_i2c5>;
405 pinctrl-1 = <&pinctrl_i2c5_gpio>;
Marek Vasutcd7b1a82022-08-12 22:41:55 +0200[diff] [blame]406 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
407 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Marek Vasutf670cd72022-05-21 16:56:26 +0200[diff] [blame]408 status = "okay";
409};
410
411&pwm1 {
412 pinctrl-0 = <&pinctrl_pwm1>;
413 pinctrl-names = "default";
414 status = "disabled";
415};
416
417&uart1 {
418 /* CA53 console */
419 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_uart1>;
421 status = "okay";
422};
423
424&uart2 {
425 /* Bluetooth */
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_uart2>;
428 uart-has-rtscts;
429 status = "okay";
430};
431
432&uart3 {
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_uart3>;
435 uart-has-rtscts;
436 status = "okay";
437};
438
439&uart4 {
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_uart4>;
442 status = "okay";
443};
444
445&usb3_phy0 {
446 status = "okay";
447};
448
449&usb3_0 {
450 status = "okay";
451};
452
453&usb_dwc3_0 {
454 pinctrl-names = "default";
455 pinctrl-0 = <&pinctrl_usb0_vbus>;
456 dr_mode = "otg";
457 status = "okay";
458};
459
460&usb3_phy1 {
461 status = "okay";
462};
463
464&usb3_1 {
465 status = "okay";
466};
467
468&usb_dwc3_1 {
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_usb1_vbus>;
471 dr_mode = "host";
472 status = "okay";
473};
474
475/* SDIO WiFi */
476&usdhc1 {
477 pinctrl-names = "default", "state_100mhz", "state_200mhz";
478 pinctrl-0 = <&pinctrl_usdhc1>;
479 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
480 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
481 vmmc-supply = <&buck4>;
482 bus-width = <4>;
483 non-removable;
484 cap-power-off-card;
485 keep-power-in-suspend;
486 status = "okay";
487
488 #address-cells = <1>;
489 #size-cells = <0>;
490
491 brcmf: bcrmf@1 { /* muRata 2AE */
492 reg = <1>;
493 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
494 /*
495 * The "host-wake" interrupt output is by default not
496 * connected to the SoC, but can be connected on to
497 * SoC pin on the carrier board.
498 */
499 reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
500 };
501};
502
503/* SD slot */
504&usdhc2 {
505 pinctrl-names = "default", "state_100mhz", "state_200mhz";
506 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
507 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
508 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
509 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
510 vmmc-supply = <&reg_usdhc2_vmmc>;
511 bus-width = <4>;
512 status = "okay";
513};
514
515/* eMMC */
516&usdhc3 {
517 pinctrl-names = "default", "state_100mhz", "state_200mhz";
518 pinctrl-0 = <&pinctrl_usdhc3>;
519 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
520 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
521 vmmc-supply = <&buck4>;
522 vqmmc-supply = <&buck5>;
523 bus-width = <8>;
524 non-removable;
525 status = "okay";
526};
527
528&wdog1 {
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_wdog>;
531 fsl,ext-reset-output;
532 status = "okay";
533};
534
535&iomuxc {
536 pinctrl-0 = <&pinctrl_hog_base
537 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
538 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
539 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
540 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
541 /* GPIO_M is connected to CLKOUT2 */
542 &pinctrl_dhcom_int>;
543 pinctrl-names = "default";
544
545 pinctrl_dhcom_a: dhcom-a-grp {
546 fsl,pins = <
547 /* ENET_QOS_EVENT0-OUT */
548 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2
549 >;
550 };
551
552 pinctrl_dhcom_b: dhcom-b-grp {
553 fsl,pins = <
554 /* ENET_QOS_EVENT0-IN */
555 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2
556 >;
557 };
558
559 pinctrl_dhcom_c: dhcom-c-grp {
560 fsl,pins = <
561 /* GPIO_C */
562 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2
563 >;
564 };
565
566 pinctrl_dhcom_d: dhcom-d-grp {
567 fsl,pins = <
568 /* GPIO_D */
569 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2
570 >;
571 };
572
573 pinctrl_dhcom_e: dhcom-e-grp {
574 fsl,pins = <
575 /* GPIO_E */
576 MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2
577 >;
578 };
579
580 pinctrl_dhcom_f: dhcom-f-grp {
581 fsl,pins = <
582 /* GPIO_F */
583 MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2
584 >;
585 };
586
587 pinctrl_dhcom_g: dhcom-g-grp {
588 fsl,pins = <
589 /* GPIO_G */
590 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2
591 >;
592 };
593
594 pinctrl_dhcom_h: dhcom-h-grp {
595 fsl,pins = <
596 /* GPIO_H */
597 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2
598 >;
599 };
600
601 pinctrl_dhcom_i: dhcom-i-grp {
602 fsl,pins = <
603 /* CSI1_SYNC */
604 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
605 >;
606 };
607
608 pinctrl_dhcom_j: dhcom-j-grp {
609 fsl,pins = <
610 /* CSIx_#RST */
611 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2
612 >;
613 };
614
615 pinctrl_dhcom_k: dhcom-k-grp {
616 fsl,pins = <
617 /* CSIx_PWDN */
618 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2
619 >;
620 };
621
622 pinctrl_dhcom_l: dhcom-l-grp {
623 fsl,pins = <
624 /* CSI2_SYNC */
625 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2
626 >;
627 };
628
629 pinctrl_dhcom_int: dhcom-int-grp {
630 fsl,pins = <
631 /* INT_HIGHEST_PRIO */
632 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2
633 >;
634 };
635
636 pinctrl_hog_base: dhcom-hog-base-grp {
637 fsl,pins = <
638 /* GPIOs for memory coding */
639 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080
640 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080
641 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080
642 /* GPIOs for hardware coding */
643 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080
644 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080
645 MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080
646 >;
647 };
648
649 pinctrl_ecspi1: dhcom-ecspi1-grp {
650 fsl,pins = <
Marek Vasuteee69bd2022-08-12 22:41:54 +0200[diff] [blame]651 MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x44
652 MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x44
653 MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x44
654 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x40
Marek Vasutf670cd72022-05-21 16:56:26 +0200[diff] [blame]655 >;
656 };
657
658 pinctrl_ecspi2: dhcom-ecspi2-grp {
659 fsl,pins = <
660 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
661 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
662 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
663 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
664 >;
665 };
666
667 pinctrl_eqos: dhcom-eqos-grp { /* RGMII */
668 fsl,pins = <
669 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
670 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
671 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
672 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
673 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
674 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
675 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
676 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
677 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
678 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
679 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
680 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
681 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
682 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
683 >;
684 };
685
686 pinctrl_enet_vio: dhcom-enet-vio-grp {
687 fsl,pins = <
688 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
689 >;
690 };
691
692 pinctrl_ethphy0: dhcom-ethphy0-grp {
693 fsl,pins = <
694 /* ENET1_#RST Reset */
695 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
696 /* ENET1_#INT Interrupt */
697 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22
698 >;
699 };
700
701 pinctrl_ethphy1: dhcom-ethphy1-grp {
702 fsl,pins = <
703 /* ENET1_#RST Reset */
704 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11
705 /* ENET1_#INT Interrupt */
706 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11
707 >;
708 };
709
710 pinctrl_fec: dhcom-fec-grp {
711 fsl,pins = <
712 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f
713 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
714 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
715 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
716 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
717 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
718 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
719 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
720 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
721 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
722 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
723 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
724 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
725 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
726 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
727 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f
728 >;
729 };
730
731 pinctrl_flexcan1: dhcom-flexcan1-grp {
732 fsl,pins = <
733 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
734 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
735 >;
736 };
737
738 pinctrl_flexcan2: dhcom-flexcan2-grp {
739 fsl,pins = <
740 MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154
741 MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154
742 >;
743 };
744
745 pinctrl_flexspi: dhcom-flexspi-grp {
746 fsl,pins = <
747 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
748 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
749 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
750 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
751 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
752 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
753 >;
754 };
755
756 pinctrl_hdmi: dhcom-hdmi-grp {
757 fsl,pins = <
758 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154
759 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154
760 >;
761 };
762
763 pinctrl_i2c3: dhcom-i2c3-grp {
764 fsl,pins = <
765 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084
766 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084
767 >;
768 };
769
770 pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
771 fsl,pins = <
772 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84
773 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84
774 >;
775 };
776
777 pinctrl_i2c4: dhcom-i2c4-grp {
778 fsl,pins = <
779 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084
780 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084
781 >;
782 };
783
784 pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
785 fsl,pins = <
786 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84
787 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84
788 >;
789 };
790
791 pinctrl_i2c5: dhcom-i2c5-grp {
792 fsl,pins = <
Marcel Ziswilercdfde792022-11-07 22:22:39 +0100[diff] [blame]793 MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084
794 MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084
Marek Vasutf670cd72022-05-21 16:56:26 +0200[diff] [blame]795 >;
796 };
797
798 pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
799 fsl,pins = <
800 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84
801 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84
802 >;
803 };
804
805 pinctrl_pmic: dhcom-pmic-grp {
806 fsl,pins = <
807 /* PMIC_nINT */
808 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
809 >;
810 };
811
812 pinctrl_pwm1: dhcom-pwm1-grp {
813 fsl,pins = <
814 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6
815 >;
816 };
817
818 pinctrl_rtc: dhcom-rtc-grp {
819 fsl,pins = <
820 /* RTC_#INT Interrupt */
Marcel Ziswilercdfde792022-11-07 22:22:39 +0100[diff] [blame]821 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080
Marek Vasutf670cd72022-05-21 16:56:26 +0200[diff] [blame]822 >;
823 };
824
825 pinctrl_touch: dhcom-touch-grp {
826 fsl,pins = <
827 /* #TOUCH_INT */
828 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080
829 >;
830 };
831
832 pinctrl_uart1: dhcom-uart1-grp {
833 fsl,pins = <
834 /* Console UART */
835 MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49
836 MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49
837 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49
838 MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49
839 >;
840 };
841
842 pinctrl_uart2: dhcom-uart2-grp {
843 fsl,pins = <
844 /* Bluetooth UART */
845 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
846 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
847 MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49
848 MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
849 >;
850 };
851
852 pinctrl_uart3: dhcom-uart3-grp {
853 fsl,pins = <
854 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49
855 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49
856 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49
857 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49
858 >;
859 };
860
861 pinctrl_uart4: dhcom-uart4-grp {
862 fsl,pins = <
863 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
864 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
865 >;
866 };
867
868 pinctrl_usb0_vbus: dhcom-usb0-grp {
869 fsl,pins = <
870 MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0
871 >;
872 };
873
874 pinctrl_usb1_vbus: dhcom-usb1-grp {
875 fsl,pins = <
876 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6
877 MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80
878 >;
879 };
880
881 pinctrl_usdhc1: dhcom-usdhc1-grp {
882 fsl,pins = <
883 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
884 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
885 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
886 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
887 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
888 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
889 /* BT_REG_EN */
890 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
891 /* WL_REG_EN */
892 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
893 >;
894 };
895
896 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
897 fsl,pins = <
898 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
899 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
900 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
901 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
902 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
903 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
904 /* BT_REG_EN */
905 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
906 /* WL_REG_EN */
907 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
908 >;
909 };
910
911 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
912 fsl,pins = <
913 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
914 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
915 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
916 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
917 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
918 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
919 /* BT_REG_EN */
920 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
921 /* WL_REG_EN */
922 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
923 >;
924 };
925
926 pinctrl_usdhc2: dhcom-usdhc2-grp {
927 fsl,pins = <
928 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
929 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
930 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
931 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
932 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
933 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
934 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
935 >;
936 };
937
938 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
939 fsl,pins = <
940 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
941 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
942 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
943 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
944 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
945 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
946 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
947 >;
948 };
949
950 pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
951 fsl,pins = <
952 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
953 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
954 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
955 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
956 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
957 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
958 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
959 >;
960 };
961
962 pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
963 fsl,pins = <
964 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20
965 >;
966 };
967
968 pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
969 fsl,pins = <
970 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080
971 >;
972 };
973
974 pinctrl_usdhc3: dhcom-usdhc3-grp {
975 fsl,pins = <
976 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
977 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
978 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
979 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
980 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
981 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
982 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
983 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
984 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
985 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
986 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
987 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
988 >;
989 };
990
991 pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
992 fsl,pins = <
993 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
994 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
995 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
996 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
997 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
998 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
999 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1000 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1001 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1002 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1003 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1004 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
1005 >;
1006 };
1007
1008 pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1009 fsl,pins = <
1010 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1011 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1012 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1013 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1014 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1015 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1016 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1017 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1018 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1019 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1020 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1021 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
1022 >;
1023 };
1024
1025 pinctrl_wdog: dhcom-wdog-grp {
1026 fsl,pins = <
1027 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
1028 >;
1029 };
1030};